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spi读取胡乱修复，

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This commit is contained in:
RuigeLee
2025-05-17 12:20:07 +08:00
parent 784bad548a
commit c4daca834c
3 changed files with 75 additions and 54 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -406,7 +406,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
))
datar := MuxCase( 0.U, Array(
((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrSel), 0.U, isEnR ),
((addrSel & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrSel),
((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
((addrSel & "hFF00".U) === "h1000".U) -> 0.U,
((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -585,7 +585,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
// io.lvds.isEnW = Output(Bool())
// io.lvds.isEnR = Output(Bool())
io.lvds.datar := RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
io.lvds.datar := AcquireReg(addr = io.lvds.addrSel)
when( io.lvds.isEnW & isSlvMode ){

45
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -48,7 +48,7 @@ abstract class SpiInterfaceBase extends Module{
val addrSel = Reg(UInt(16.W)); io.addrSel := addrSel
val addrSel = Reg(UInt(16.W))
val spiCmd = Reg(UInt(8.W))
val isSpiWrite = spiCmd === 0.U
@@ -58,9 +58,14 @@ abstract class SpiInterfaceBase extends Module{
val byteSel = Reg(UInt(12.W))
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exReg === 1.U & byteSel === 3.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U)
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg
io.addrSel :=
Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
when( shiftCSn(2) & ~shiftCSn(1) ){
byteSel := 0.U
@@ -114,18 +119,12 @@ class SSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
exReg := 0.U
} .elsewhen( isSpiRead ){
exReg := io.datar
} .otherwise{
assert(false.B, "Assert Failed, empty CMD!\n")
}
}
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & (byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
exReg := 0.U
} .elsewhen( isSpiWrite ){
exReg := 0.U
} .elsewhen( isSpiRead ){
exReg := io.datar
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
}
@@ -150,18 +149,12 @@ class QSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
exReg := 0.U
} .elsewhen( isSpiRead ){
exReg := io.datar
} .otherwise{
assert(false.B, "Assert Failed, empty CMD!\n")
}
}
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & ( byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
exReg := 0.U
} .elsewhen( io.isEnW ){
exReg := 0.U
} .elsewhen( io.isEnR ){
exReg := io.datar
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(3,0), shiftMOSI(1) )
}