From c40980bf2f1b3f40a0f68ffb5b1389cea23d2d27 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Mon, 24 Jun 2024 11:18:47 +0800 Subject: [PATCH] =?UTF-8?q?=E7=AD=89=E5=BE=85=E6=96=87=E6=A1=A3=E6=9B=B4?= =?UTF-8?q?=E6=96=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/Qei.scala | 129 ++++++++++++++++++++++++++ src/main/scala/backBoard/Qei.scala.bk | 49 ---------- 2 files changed, 129 insertions(+), 49 deletions(-) create mode 100644 src/main/scala/backBoard/Qei.scala delete mode 100644 src/main/scala/backBoard/Qei.scala.bk diff --git a/src/main/scala/backBoard/Qei.scala b/src/main/scala/backBoard/Qei.scala new file mode 100644 index 0000000..e876cae --- /dev/null +++ b/src/main/scala/backBoard/Qei.scala @@ -0,0 +1,129 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +trait BackBoardSlvQei{ this: BackBoardSlvLocal => + val phaseA = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val phaseB = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val counter = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } + val encordNxt = for( i <- 0 until 2 ) yield { Cat( phaseB(i), phaseA(i) ) } + val encordCur = for( i <- 0 until 2 ) yield { RegNext(encordNxt) } + + val isEnable = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isSign = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isInit = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val initVal = for( i <- 0 until 2 ) yield { Wire(UInt(32.W)) } + val mode = for( i <- 0 until 2 ) yield { Wire(UInt(2.W)) } + val overflow = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val invDirect = for( i <- 0 until 2 ) yield { Wire(Bool()) } + + + + val isAdvA = for( i <- 0 until 2 ) yield { + ( encordCur(i) === "b00".U & encordNxt(i) === "b01".U & mode(i).extract(1)) | + ( encordCur(i) === "b01".U & encordNxt(i) === "b11".U & mode(i) =/= "b00".U ) | + ( encordCur(i) === "b11".U & encordNxt(i) === "b10".U & mode(i).extract(1)) | + ( encordCur(i) === "b10".U & encordNxt(i) === "b00".U ) + } + + + val isAdvB = for( i <- 0 until 2 ) yield { + ( encordNxt(i) === "b00".U & encordCur(i) === "b01".U ) | + ( encordNxt(i) === "b01".U & encordCur(i) === "b11".U & mode(i).extract(1)) | + ( encordNxt(i) === "b11".U & encordCur(i) === "b10".U & mode(i) =/= "b00".U ) | + ( encordNxt(i) === "b10".U & encordCur(i) === "b00".U & mode(i).extract(1)) + } + + val isMiss = for( i <- 0 until 2 ) yield { encordCur(i) === ~encordNxt(i) } + val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) === encordNxt(i) } + val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) } + + for( i <- 0 until 2 ){ + + + isOverflow(i) := false.B + when(isEnable(i)){ + when( isMiss(i) ){ + printf("Warning! QEI Miss one pulse!\n") + } .elsewhen( isAdvA(i) ){ + when( isSign(i) ) { + when( invDirect(i) ){ + when( overflow & counter(i) === "h80000000".U ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) - 1.U + } + } .otherwise{ + when( overflow & counter(i) === "h7FFFFFFF".U ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) + 1.U + } + } + } .otherwise{ + when( invDirect(i) ){ + when( overflow & counter(i) === 0.U ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) - 1.U + } + } .otherwise{ + when( overflow & counter(i) === "hFFFFFFFF.U" ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) + 1.U + } + } + } + } .elsewhen( isAdvB(i) ){ + when( isSign(i) ) { + when( invDirect(i) ){ + when( overflow & counter(i) === "h7FFFFFFF".U ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) + 1.U + } + } .otherwise{ + when( overflow & counter(i) === "h80000000".U ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) - 1.U + } + } + } .otherwise{ + when( invDirect(i) ){ + when( overflow & counter(i) === "hFFFFFFFF.U" ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) + 1.U + } + } .otherwise{ + when( overflow & counter(i) === 0.U ){ + counter(i) := counter(i) + isOverflow(i) := true.B + } .otherwise{ + counter(i) := counter(i) - 1.U + } + } + } + } .otherwise{ + assert( isKeep(i) ) + } + } + + + } + + +} + + diff --git a/src/main/scala/backBoard/Qei.scala.bk b/src/main/scala/backBoard/Qei.scala.bk deleted file mode 100644 index a211824..0000000 --- a/src/main/scala/backBoard/Qei.scala.bk +++ /dev/null @@ -1,49 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - - -trait BackBoardSlvQei{ this: BackBoardSlvLocal => - val phaseA = Wire(Bool()) - val phaseB = Wire(Bool()) - - - - val counter = Reg(UInt(32.W)) - - val encordNxt = Cat( phaseB, phaseA ) - val encordCur = RegNext(encordNxt) - - val isCheckDirect = Wire(Bool()) - val is2Multi = Wire(Bool()) - val is4Multi = Wire(Bool()) - - val isAdvA = - ( encordCur === "b00".U & encordNxt === "b01".U ) | - ( encordCur === "b01".U & encordNxt === "b11".U ) | - ( encordCur === "b11".U & encordNxt === "b10".U ) | - ( encordCur === "b10".U & encordNxt === "b00".U ) - - val isAdvB = - ( encordNxt === "b00".U & encordCur === "b01".U ) | - ( encordNxt === "b01".U & encordCur === "b11".U ) | - ( encordNxt === "b11".U & encordCur === "b10".U ) | - ( encordNxt === "b10".U & encordCur === "b00".U ) - - val isMiss = encordCur === ~encordNxt - val isKeep = encordCur === encordNxt - - when(){ - when( isMiss ){ - printf("Warning! QEI Miss one pulse!\n") - } .elsewhen( isAdvA ){ - - } .elsewhen( isAdvB ){ - - } .otherwise{ - assert( isKeep ) - } - } - -} \ No newline at end of file