修复spicmd没有在每次传输前后复位地问题,或许将导致三态门状态错误

This commit is contained in:
RuigeLee
2025-09-08 17:02:43 +08:00
parent 955fda6d05
commit c3c3a25e77

View File

@@ -44,22 +44,22 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1) val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B) val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
val exRego = Reg(UInt(8.W)) val exRego = RegInit(0.U(8.W))
val exRegi = Reg(UInt(8.W)) val exRegi = RegInit(0.U(8.W))
val addrw = RegInit(0.U(16.W)) val addrw = RegInit(0.U(16.W))
val addrr = RegInit(0.U(16.W)) val addrr = RegInit(0.U(16.W))
val spiCmd = Reg(UInt(1.W)) val spiCmd = RegInit(0.U(1.W))
val isSpiWrite = spiCmd === 0.U val isSpiWrite = spiCmd === 0.U
val isSpiRead = spiCmd === 1.U val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W)) val bitSel = RegInit(0.U(3.W))
val bitSelNext = RegNext(bitSel) val bitSelNext = RegNext(bitSel, 0.U(3.W))
val byteSel = Reg(UInt(12.W)) val byteSel = RegInit(0.U(12.W))
val byteSelNext = RegNext(byteSel) val byteSelNext = RegNext(byteSel, 0.U(12.W))
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
@@ -93,7 +93,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
class SSpiInterface extends SpiInterfaceBase{ class SSpiInterface extends SpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO) val spi = IO(new SSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(spi.mosi, 3) val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
sck := spi.sck sck := spi.sck
csn := spi.csn csn := spi.csn
@@ -103,7 +103,9 @@ class SSpiInterface extends SpiInterfaceBase{
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === 1.U & byteSelNext === 2.U ) | (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === 1.U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U) (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低且SCK上跳的第0byte when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低且SCK上跳的第0byte
spiCmd := shiftMOSI(1) spiCmd := shiftMOSI(1)
} }
@@ -111,7 +113,7 @@ class SSpiInterface extends SpiInterfaceBase{
spi.miso := exRego.extract(7) spi.miso := exRego.extract(7)
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U bitSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
bitSel := bitSel + 1.U bitSel := bitSel + 1.U
} }
@@ -127,7 +129,7 @@ class SSpiInterface extends SpiInterfaceBase{
} }
} }
//输出在SCK下降沿准备数据 //输出在SCK上升沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0 exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){
@@ -167,12 +169,11 @@ class SSpiInterface extends SpiInterfaceBase{
} }
} }
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
} }
class QSpiInterface extends SpiInterfaceBase{ class QSpiInterface extends SpiInterfaceBase{
val qspi = IO(new QSPIInterfaceIO) val qspi = IO(new QSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3) val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
sck := qspi.sck sck := qspi.sck
csn := qspi.csn csn := qspi.csn
@@ -183,7 +184,9 @@ class QSpiInterface extends SpiInterfaceBase{
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(2) === "b1000".U & byteSelNext === 2.U ) | (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(2) === "b1000".U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U) (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低且SCK上跳的第0byte when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低且SCK上跳的第0byte
spiCmd := shiftMOSI(2).extract(3) spiCmd := shiftMOSI(2).extract(3)
} }
@@ -193,10 +196,6 @@ class QSpiInterface extends SpiInterfaceBase{
bitSel := ~bitSel bitSel := ~bitSel
} }
//输入看SCK上升沿 //输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){ when( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){ when( bitSel === 0.U ){
@@ -206,7 +205,7 @@ class QSpiInterface extends SpiInterfaceBase{
} }
} }
//输出在SCK下降沿准备数据 //输出在SCK上升沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0 exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){ } .elsewhen( isSckPosedge & ~shiftCSn(1) ){