定向数据流已清
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@@ -29,14 +29,16 @@ class Robin(implicit p: Parameters) extends SwitchModule{
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val isLock = RegInit(false.B)
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val lockChn = Reg(UInt((log2Ceil(chn+1)).W))
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val lfsr = LFSR(chn+1, ~isLock)
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val lfsr = ~LFSR( log2Ceil(chn+1), ~isLock)
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for( i <- 0 until chn+1 ) {
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when( i.U === lfsr ){
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when( io.enq(i).mInfo.dest.valid ){
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assert( ~isLock )
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isLock := true.B
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isLock := true.B
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lockChn := lfsr
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}
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}
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}
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@@ -58,7 +60,7 @@ class Robin(implicit p: Parameters) extends SwitchModule{
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io.deq.mInfo.source.valid := false.B
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io.deq.mInfo.source.bits := 0.U
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} .otherwise{
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io.deq <> io.enq(lfsr)
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io.deq <> io.enq(lockChn)
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}
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