定向数据流已清

2023-11-08 15:41:21 +08:00
parent 99d3490173
commit c31479f898
5 changed files with 19 additions and 9 deletions
--- a/src/main/scala/Switch/DMA.scala
+++ b/src/main/scala/Switch/DMA.scala
@@ -82,7 +82,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
  val mInfoValid = stateCur === stateTx

  when( rxBuff.mInfo.source.valid & stateCur === stateIdle & stateNxt === stateRx  ){
-    assert( rxBuff.mInfo.source.bits(48) === 1.U )
+    // assert( rxBuff.mInfo.source.bits(48) === 1.U )
    trigRxNum := rxBuff.mInfo.source.bits
    dmaAddress := io.sel(rxBuff.mInfo.source.bits( log2Ceil(chn)-1, 0 )).r_RxPtr
  }