定向数据流已清

src/main/scala/Switch/DMA.scala

@@ -82,7 +82,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
   val mInfoValid = stateCur === stateTx
 
   when( rxBuff.mInfo.source.valid & stateCur === stateIdle & stateNxt === stateRx  ){
-    assert( rxBuff.mInfo.source.bits(48) === 1.U )
+    // assert( rxBuff.mInfo.source.bits(48) === 1.U )
     trigRxNum := rxBuff.mInfo.source.bits
     dmaAddress := io.sel(rxBuff.mInfo.source.bits( log2Ceil(chn)-1, 0 )).r_RxPtr
   }

src/main/scala/Switch/PiPoBuff.scala

@@ -54,8 +54,10 @@ class PiPoBuffBase[T<:Data]( dp: Int, val threshold: Int = 32) extends Module{
 
 
   when( io.enq.fire ){
-    when( io.enq.bits.isStart ){
+    when( io.enq.bits.isLast ){
       cnt := 0.U      
+    } .elsewhen( io.enq.bits.isStart ){
+      cnt := 1.U      
     } .otherwise{
       cnt := cnt + 1.U
     }

src/main/scala/Switch/Robin.scala

@@ -29,14 +29,16 @@ class Robin(implicit p: Parameters) extends SwitchModule{
 
 
   val isLock = RegInit(false.B)
+  val lockChn = Reg(UInt((log2Ceil(chn+1)).W))
 
-  val lfsr = LFSR(chn+1, ~isLock)
+  val lfsr = ~LFSR( log2Ceil(chn+1), ~isLock)
 
   for( i <- 0 until chn+1 ) {
     when( i.U === lfsr ){
       when( io.enq(i).mInfo.dest.valid ){
         assert( ~isLock )
-        isLock := true.B
+        isLock  := true.B
+        lockChn := lfsr
       }
     }
   }
@@ -58,7 +60,7 @@ class Robin(implicit p: Parameters) extends SwitchModule{
     io.deq.mInfo.source.valid := false.B
     io.deq.mInfo.source.bits  := 0.U
   } .otherwise{
-    io.deq <> io.enq(lfsr)
+    io.deq <> io.enq(lockChn)
   }
 
 

src/main/scala/Switch/Switch.scala

@@ -105,8 +105,8 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
   when( robin.io.deq.rx.fire & robin.io.deq.rx.bits.isLast ){
     assert( isMuxBusy )
     isMuxBusy := false.B
-  } .elsewhen( robin.io.deq.mInfo.dest.valid ){
-    assert( ~isMuxBusy )
+  } .elsewhen( robin.io.deq.mInfo.dest.valid & ~isMuxBusy ){
+
     isMuxBusy := true.B
 
 

src/main/scala/Switch/mac/MacTx.scala

@@ -130,7 +130,7 @@ trait MacTxFSM { this: MacTxBase =>
     StatePreamble := true.B
   }
 
-  when(StartFCS | StartJam){
+  when(StartFCS | StartJam | StartDefer){
     StatePAD := false.B
   }.elsewhen(StartPAD){
     StatePAD := true.B
@@ -287,7 +287,13 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
 
   io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS)
   val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
-  io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & NibbleMinFl & ~io.CrcEn)
+
+  io.StartTxDone :=
+    ~io.Collision &
+      ( (StateFCS & NibCntEq7) |
+        (StateData(1) & io.TxEndFrm & NibbleMinFl & ~io.CrcEn) |
+        (StatePAD                   & NibbleMinFl & ~io.CrcEn) )
+
   io.LateCollision := StartJam & ~ColWindow
   io.MaxCollisionOccured := StartJam & ColWindow;
   StateSFD := StatePreamble & NibCntEq15;