diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 8bc4c1e..bfd9801 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -89,7 +89,7 @@ abstract class SpiInterfaceBase extends Module{
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
     addrw := exRegi
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
-    addrw := Cat(exRegi, addrw(7,0))
+    addrw := Cat(addrw(7,0), exRegi)
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
       addrw := addrw + 1.U
@@ -101,7 +101,7 @@ abstract class SpiInterfaceBase extends Module{
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
     addrr := exRegi
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
-    addrr := Cat(exRegi, addrr(7,0))
+    addrr := Cat(addrr(7,0), exRegi)
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
       addrr := addrr + 1.U
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index c61d79b..be4d92b 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -400,8 +400,8 @@ end
 //sidx为0~4；外部spi为5~9，外部qspi为10~15
 task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx );
   begin
-    txBuf[0] <= saddress[7:0];
-    txBuf[1] <= saddress[15:8];
+    txBuf[0] <= saddress[15:8];
+    txBuf[1] <= saddress[7:0];
     txBuf[2] <= scmd;
 
     length <= slength + 3;