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update sram; bug fixed; lvds failed

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This commit is contained in:
RuigeLee
2023-08-23 19:32:41 +08:00
parent cead446356
commit c0645cfe16
2 changed files with 102 additions and 79 deletions
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22
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -3,6 +3,9 @@ package BACK
import chisel3._
import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
val addr = Input(UInt(13.W))
@@ -35,8 +38,8 @@ class BackBoardMstBase extends RawModule{
val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAM)
val mirrorUp = Module(new MirrorSRAM)
val mirrorDown = Module(new MirrorSRAM(8, 2048))
val mirrorUp = Module(new MirrorSRAM(8, 2048))
val status = Wire(UInt(8.W))
val slvNum = Wire(UInt(5.W))
@@ -66,12 +69,16 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
io.FSMC.dataOEn := io.FSMC.oen
mirrorDown.io.we := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.enw := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.addrw := fsmcAddrSync(10,0)
mirrorDown.io.dataw := fsmcdataInSync
// mirrorUp.io.ce := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.enr := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.addrr := fsmcAddrSync(10,0)
val regOut = Wire(UInt(8.W))
@@ -113,7 +120,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val stateCur = RegInit(0.U(3.W))
val stateCur = RegInit(5.U(3.W))
val ( cnt, trigger ) = Counter(Range( 0,1023))
val addrr = RegInit(0.U)
@@ -204,10 +211,13 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
addrw := addrw + 1.U
}
mirrorDown.io.enr := (stateCur === 3.U || stateCur === 4.U)
lvdsMst.io.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr
mirrorUp.io.we := lvdsMst.io.rx_data_valid
mirrorUp.io.enw := lvdsMst.io.rx_data_valid
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw

153
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -4,89 +4,102 @@ import chisel3._
import chisel3.util._
class MirrorSRAM(dw: Int, cl: Int) extends RawModule {
def line_w = log2Ceil(cl)
val io = IO(new Bundle{
val addrr = Input(UInt(line_w.W))
val addrw = Input(UInt(line_w.W))
val dataw = Input( UInt(dw.W) )
val datar = Output( UInt(dw.W) )
val enw = Input(Bool())
val enr = Input(Bool())
class MirrorSRAMIO extends Bundle{
val datar = Output(UInt(8.W))
val dataw = Input(UInt(8.W))
val clock = Input(Bool())
val reset = Input(Bool())
val we = Input(Bool())
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(11.W))
})
// val datar_a = Output(UInt(8.W))
// val datar_b = Output(UInt(8.W))
withClockAndReset( io.clock.asClock, io.reset ){
val mem = SyncReadMem( cl, UInt(dw.W) )
// val clk_a = Input(Bool())
// val clk_b = Input(Bool())
// val reset_a = Input(Bool())
// val reset_b = Input(Bool())
// val ce_a = Input(Bool())
// val ce_b = Input(Bool())
// val we_a = Input(Bool())
// val we_b = Input(Bool())
// val addr_a = Input(UInt(11.W))
// val addr_b = Input(UInt(11.W))
// val dataw_a = Input(UInt(8.W))
// val dataw_b = Input(UInt(8.W))
io.datar := DontCare
when( io.enr ) {
io.datar := mem.read( io.addrr )
}
when( io.enw ) {
mem.write( io.addrw, io.dataw )
}
}
class MirrorSRAM extends BlackBox with HasBlackBoxInline {
val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
setInline("microSRAM.v",
"""
| module MirrorSRAM(
| output [7:0] datar,
| input [7:0] dataw,
|
| input clock,
| input reset,
|
| input we,
|
| input [11:0] addrw,
| input [11:0] addrr
|
| );
|
| wire [31:0] dout;
| assign datar = dout[7:0];
|
|
|SDPB bram_sdpb_0 (
| .DO({dout[31:8],dout[7:0]}),
| .CLKA(clock),
| .CEA(we),
| .RESETA(reset),
| .CLKB(clock),
| .CEB(1'b1),
| .RESETB(reset),
| .OCE(1'b1),
| .BLKSELA(3'b0),
| .BLKSELB(3'b0),
| .ADA({addrw,3'b0}),
| .DI({24'b0, dataw}),
| .ADB({addrr,3'b0})
| );
| defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
| defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
| defparam bram_sdpb_0.RESET_MODE = "SYNC";
|
|endmodule
""".stripMargin)
}
// class MirrorSRAMIO extends Bundle{
// val datar = Output(UInt(8.W))
// val dataw = Input(UInt(8.W))
// val clock = Input(Bool())
// val reset = Input(Bool())
// val we = Input(Bool())
// val addrr = Input(UInt(11.W))
// val addrw = Input(UInt(11.W))
// }
// class MirrorSRAM extends BlackBox with HasBlackBoxInline {
// val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
// setInline("microSRAM.v",
// """
// | module MirrorSRAM(
// | output [7:0] datar,
// | input [7:0] dataw,
// |
// | input clock,
// | input reset,
// |
// | input we,
// |
// | input [11:0] addrw,
// | input [11:0] addrr
// |
// | );
// |
// | wire [31:0] dout;
// | assign datar = dout[7:0];
// |
// |
// |SDPB bram_sdpb_0 (
// | .DO({dout[31:8],dout[7:0]}),
// | .CLKA(clock),
// | .CEA(we),
// | .RESETA(reset),
// | .CLKB(clock),
// | .CEB(1'b1),
// | .RESETB(reset),
// | .OCE(1'b1),
// | .BLKSELA(3'b0),
// | .BLKSELB(3'b0),
// | .ADA({addrw,3'b0}),
// | .DI({24'b0, dataw}),
// | .ADB({addrr,3'b0})
// | );
// | defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
// | defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
// | defparam bram_sdpb_0.RESET_MODE = "SYNC";
// |
// |endmodule
// """.stripMargin)
// }