update sram; bug fixed; lvds failed

src/main/scala/backBoard/BackBoardMst.scala

@@ -3,6 +3,9 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+
+
+
 class FSMC_Port_Bundle extends Bundle{
 
   val addr    = Input(UInt(13.W))
@@ -35,8 +38,8 @@ class BackBoardMstBase extends RawModule{
 
 
   val lvdsMst = Module(new Lvds_Bus_Master)
-  val mirrorDown = Module(new MirrorSRAM)
+  val mirrorDown = Module(new MirrorSRAM(8, 2048))
-  val mirrorUp = Module(new MirrorSRAM)
+  val mirrorUp   = Module(new MirrorSRAM(8, 2048))
 
     val status  = Wire(UInt(8.W))
     val slvNum  = Wire(UInt(5.W))
@@ -66,12 +69,16 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     io.FSMC.dataOEn := io.FSMC.oen
 
 
-    mirrorDown.io.we    := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
+
+
+
+  
+    mirrorDown.io.enw    := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
     mirrorDown.io.addrw  := fsmcAddrSync(10,0)
     mirrorDown.io.dataw := fsmcdataInSync
 
     
-    // mirrorUp.io.ce    := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
+    mirrorUp.io.enr    := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
     mirrorUp.io.addrr  := fsmcAddrSync(10,0)
 
     val regOut = Wire(UInt(8.W))
@@ -113,7 +120,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
 
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
 
-    val stateCur = RegInit(0.U(3.W))
+    val stateCur = RegInit(5.U(3.W))
     val ( cnt, trigger ) = Counter(Range( 0,1023))
 
     val addrr = RegInit(0.U)
@@ -204,10 +211,13 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
       addrw := addrw + 1.U
     }
 
+
+
+    mirrorDown.io.enr := (stateCur === 3.U || stateCur === 4.U)
     lvdsMst.io.tx_data_in := mirrorDown.io.datar
     mirrorDown.io.addrr := addrr
     
-    mirrorUp.io.we    := lvdsMst.io.rx_data_valid
+    mirrorUp.io.enw    := lvdsMst.io.rx_data_valid
     mirrorUp.io.dataw := lvdsMst.io.rx_data_out
     mirrorUp.io.addrw := addrw
 

src/main/scala/backBoard/MirrorSRAM.scala

@@ -4,89 +4,102 @@ import chisel3._
 import chisel3.util._
 
 
+class MirrorSRAM(dw: Int,  cl: Int) extends RawModule {
+  def line_w   = log2Ceil(cl)
+  val io = IO(new Bundle{
+    val addrr  = Input(UInt(line_w.W))
+    val addrw  = Input(UInt(line_w.W))
 
+    val dataw = Input( UInt(dw.W) )
+    val datar = Output( UInt(dw.W) )
+    val enw   = Input(Bool())
+    val enr   = Input(Bool())
 
-
-
-
-
-
-class MirrorSRAMIO extends Bundle{
-  val datar = Output(UInt(8.W))
-  val dataw = Input(UInt(8.W))
     val clock = Input(Bool())
     val reset = Input(Bool())
-  val we = Input(Bool())
+  })
-  val addrr = Input(UInt(11.W))
-  val addrw = Input(UInt(11.W))
 
 
-  // val datar_a = Output(UInt(8.W))
+  withClockAndReset( io.clock.asClock, io.reset ){
-  // val datar_b = Output(UInt(8.W))
+    val mem = SyncReadMem( cl, UInt(dw.W) )
 
-  // val clk_a = Input(Bool())
-  // val clk_b = Input(Bool())
 
-  // val reset_a = Input(Bool())
-  // val reset_b = Input(Bool())
 
-  // val ce_a = Input(Bool())
-  // val ce_b = Input(Bool())
 
-  // val we_a = Input(Bool())
+    io.datar := DontCare
-  // val we_b = Input(Bool())
+    when( io.enr ) {
+      io.datar := mem.read( io.addrr )
+    } 
+    when( io.enw ) {
+      mem.write( io.addrw, io.dataw )
+    }
+  }
+
+
 
-  // val addr_a = Input(UInt(11.W))
-  // val addr_b = Input(UInt(11.W))
 
-  // val dataw_a = Input(UInt(8.W))
-  // val dataw_b = Input(UInt(8.W))
 }
 
-class MirrorSRAM extends BlackBox with HasBlackBoxInline {
 
-  val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
 
-  setInline("microSRAM.v",
+
-              """
+
-  |   module MirrorSRAM(
+
-  |      output [7:0] datar,
+// class MirrorSRAMIO extends Bundle{
-  |      input  [7:0] dataw,
+//   val datar = Output(UInt(8.W))
-  |
+//   val dataw = Input(UInt(8.W))
-  |      input clock,
+//   val clock = Input(Bool())
-  |      input reset,
+//   val reset = Input(Bool())
-  |
+//   val we = Input(Bool())
-  |      input we,
+//   val addrr = Input(UInt(11.W))
-  |
+//   val addrw = Input(UInt(11.W))
-  |      input [11:0] addrw,
+
-  |      input [11:0] addrr
+// }
-  |
+
-  |   );
+// class MirrorSRAM extends BlackBox with HasBlackBoxInline {
-  |
+
-  |   wire [31:0] dout; 
+//   val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
-  |   assign datar = dout[7:0];
+
-  |
+//   setInline("microSRAM.v",
-  |
+//               """
-  |SDPB bram_sdpb_0 (
+//   |   module MirrorSRAM(
-  |  .DO({dout[31:8],dout[7:0]}),
+//   |      output [7:0] datar,
-  |  .CLKA(clock),
+//   |      input  [7:0] dataw,
-  |  .CEA(we),
+//   |
-  |  .RESETA(reset),
+//   |      input clock,
-  |  .CLKB(clock),
+//   |      input reset,
-  |  .CEB(1'b1),
+//   |
-  |  .RESETB(reset),
+//   |      input we,
-  |  .OCE(1'b1),
+//   |
-  |  .BLKSELA(3'b0),
+//   |      input [11:0] addrw,
-  |  .BLKSELB(3'b0),
+//   |      input [11:0] addrr
-  |  .ADA({addrw,3'b0}),
+//   |
-  |  .DI({24'b0, dataw}),
+//   |   );
-  |  .ADB({addrr,3'b0})
+//   |
-  |  );
+//   |   wire [31:0] dout; 
-  |  defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
+//   |   assign datar = dout[7:0];
-  |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
+//   |
-  |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
+//   |
-  |
+//   |SDPB bram_sdpb_0 (
-  |endmodule
+//   |  .DO({dout[31:8],dout[7:0]}),
-    """.stripMargin)
+//   |  .CLKA(clock),
-}
+//   |  .CEA(we),
+//   |  .RESETA(reset),
+//   |  .CLKB(clock),
+//   |  .CEB(1'b1),
+//   |  .RESETB(reset),
+//   |  .OCE(1'b1),
+//   |  .BLKSELA(3'b0),
+//   |  .BLKSELB(3'b0),
+//   |  .ADA({addrw,3'b0}),
+//   |  .DI({24'b0, dataw}),
+//   |  .ADB({addrr,3'b0})
+//   |  );
+//   |  defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
+//   |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
+//   |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
+//   |
+//   |endmodule
+//     """.stripMargin)
+// }