update sram; bug fixed; lvds failed

src/main/scala/backBoard/MirrorSRAM.scala

@@ -4,89 +4,102 @@ import chisel3._
 import chisel3.util._
 
 
+class MirrorSRAM(dw: Int,  cl: Int) extends RawModule {
+  def line_w   = log2Ceil(cl)
+  val io = IO(new Bundle{
+    val addrr  = Input(UInt(line_w.W))
+    val addrw  = Input(UInt(line_w.W))
+
+    val dataw = Input( UInt(dw.W) )
+    val datar = Output( UInt(dw.W) )
+    val enw   = Input(Bool())
+    val enr   = Input(Bool())
+
+    val clock = Input(Bool())
+    val reset = Input(Bool())
+  })
+
+
+  withClockAndReset( io.clock.asClock, io.reset ){
+    val mem = SyncReadMem( cl, UInt(dw.W) )
 
 
 
 
+    io.datar := DontCare
+    when( io.enr ) {
+      io.datar := mem.read( io.addrr )
+    } 
+    when( io.enw ) {
+      mem.write( io.addrw, io.dataw )
+    }
+  }
 
 
 
-class MirrorSRAMIO extends Bundle{
-  val datar = Output(UInt(8.W))
-  val dataw = Input(UInt(8.W))
-  val clock = Input(Bool())
-  val reset = Input(Bool())
-  val we = Input(Bool())
-  val addrr = Input(UInt(11.W))
-  val addrw = Input(UInt(11.W))
 
-
-  // val datar_a = Output(UInt(8.W))
-  // val datar_b = Output(UInt(8.W))
-
-  // val clk_a = Input(Bool())
-  // val clk_b = Input(Bool())
-
-  // val reset_a = Input(Bool())
-  // val reset_b = Input(Bool())
-
-  // val ce_a = Input(Bool())
-  // val ce_b = Input(Bool())
-
-  // val we_a = Input(Bool())
-  // val we_b = Input(Bool())
-
-  // val addr_a = Input(UInt(11.W))
-  // val addr_b = Input(UInt(11.W))
-
-  // val dataw_a = Input(UInt(8.W))
-  // val dataw_b = Input(UInt(8.W))
 }
 
-class MirrorSRAM extends BlackBox with HasBlackBoxInline {
 
-  val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
 
-  setInline("microSRAM.v",
-              """
-  |   module MirrorSRAM(
-  |      output [7:0] datar,
-  |      input  [7:0] dataw,
-  |
-  |      input clock,
-  |      input reset,
-  |
-  |      input we,
-  |
-  |      input [11:0] addrw,
-  |      input [11:0] addrr
-  |
-  |   );
-  |
-  |   wire [31:0] dout; 
-  |   assign datar = dout[7:0];
-  |
-  |
-  |SDPB bram_sdpb_0 (
-  |  .DO({dout[31:8],dout[7:0]}),
-  |  .CLKA(clock),
-  |  .CEA(we),
-  |  .RESETA(reset),
-  |  .CLKB(clock),
-  |  .CEB(1'b1),
-  |  .RESETB(reset),
-  |  .OCE(1'b1),
-  |  .BLKSELA(3'b0),
-  |  .BLKSELB(3'b0),
-  |  .ADA({addrw,3'b0}),
-  |  .DI({24'b0, dataw}),
-  |  .ADB({addrr,3'b0})
-  |  );
-  |  defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
-  |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
-  |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
-  |
-  |endmodule
-    """.stripMargin)
-}
+
+
+
+// class MirrorSRAMIO extends Bundle{
+//   val datar = Output(UInt(8.W))
+//   val dataw = Input(UInt(8.W))
+//   val clock = Input(Bool())
+//   val reset = Input(Bool())
+//   val we = Input(Bool())
+//   val addrr = Input(UInt(11.W))
+//   val addrw = Input(UInt(11.W))
+
+// }
+
+// class MirrorSRAM extends BlackBox with HasBlackBoxInline {
+
+//   val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
+
+//   setInline("microSRAM.v",
+//               """
+//   |   module MirrorSRAM(
+//   |      output [7:0] datar,
+//   |      input  [7:0] dataw,
+//   |
+//   |      input clock,
+//   |      input reset,
+//   |
+//   |      input we,
+//   |
+//   |      input [11:0] addrw,
+//   |      input [11:0] addrr
+//   |
+//   |   );
+//   |
+//   |   wire [31:0] dout; 
+//   |   assign datar = dout[7:0];
+//   |
+//   |
+//   |SDPB bram_sdpb_0 (
+//   |  .DO({dout[31:8],dout[7:0]}),
+//   |  .CLKA(clock),
+//   |  .CEA(we),
+//   |  .RESETA(reset),
+//   |  .CLKB(clock),
+//   |  .CEB(1'b1),
+//   |  .RESETB(reset),
+//   |  .OCE(1'b1),
+//   |  .BLKSELA(3'b0),
+//   |  .BLKSELB(3'b0),
+//   |  .ADA({addrw,3'b0}),
+//   |  .DI({24'b0, dataw}),
+//   |  .ADB({addrr,3'b0})
+//   |  );
+//   |  defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
+//   |  defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
+//   |  defparam bram_sdpb_0.RESET_MODE = "SYNC";
+//   |
+//   |endmodule
+//     """.stripMargin)
+// }