update sram; bug fixed; lvds failed

This commit is contained in:
RuigeLee
2023-08-23 19:32:41 +08:00
parent cead446356
commit c0645cfe16
2 changed files with 102 additions and 79 deletions

View File

@@ -3,6 +3,9 @@ package BACK
import chisel3._
import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
val addr = Input(UInt(13.W))
@@ -35,8 +38,8 @@ class BackBoardMstBase extends RawModule{
val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAM)
val mirrorUp = Module(new MirrorSRAM)
val mirrorDown = Module(new MirrorSRAM(8, 2048))
val mirrorUp = Module(new MirrorSRAM(8, 2048))
val status = Wire(UInt(8.W))
val slvNum = Wire(UInt(5.W))
@@ -65,13 +68,17 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
io.FSMC.dataOEn := io.FSMC.oen
mirrorDown.io.we := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.enw := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.addrw := fsmcAddrSync(10,0)
mirrorDown.io.dataw := fsmcdataInSync
// mirrorUp.io.ce := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.enr := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.addrr := fsmcAddrSync(10,0)
val regOut = Wire(UInt(8.W))
@@ -113,7 +120,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val stateCur = RegInit(0.U(3.W))
val stateCur = RegInit(5.U(3.W))
val ( cnt, trigger ) = Counter(Range( 0,1023))
val addrr = RegInit(0.U)
@@ -204,10 +211,13 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
addrw := addrw + 1.U
}
mirrorDown.io.enr := (stateCur === 3.U || stateCur === 4.U)
lvdsMst.io.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr
mirrorUp.io.we := lvdsMst.io.rx_data_valid
mirrorUp.io.enw := lvdsMst.io.rx_data_valid
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw