diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index ced0ef3..7605471 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -47,11 +47,55 @@ trait CDRInOverSample{ this: CDRInBase =>
 
   val syncSerDat = ShiftRegister( asyncSerDat, 2 )
 
-
-
-    
 }
 
+trait CDRInMultiSample{ this: CDRInBase =>
+  val clkNum: Int = 16
+  // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
+  val sampleReg = for( i <- 0 until clkNum ) yield {
+    withClockAndReset(io.multiCLK(i).asClock, reset.asBool){ ShiftRegisters( io.serDat, 2 ) }
+  }
+
+  // val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
+  // arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
+  val arbCnt = RegInit("b1".U(clkNum.W))
+  arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(clkNum-1) )
+
+  // val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
+  // when( sampleReg(0) ^ sampleReg(1) ){
+  //   arbLock := arbCnt
+  // }
+  val arbLock = Reg(UInt( clkNum.W ))
+  when( sampleReg(0) ^ sampleReg(1) ){
+    arbLock := arbCnt
+  }
+
+
+  // val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
+  //   Mux1H(
+  //     (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
+  //       //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
+  //       ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate)
+  //     })
+  //   )
+  // )}
+
+  val asyncSerDat = 
+    Mux1H(
+      (for { i <- 0 until clkNum; j <- 0 until clkNum } yield {
+        //跳变沿到来锁定的位置        锁定拍当前所在的位置          选择锁定拍后一拍的值认为是正确值
+        ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((clkNum - 1 - i + j) % clkNum)
+      })
+    )
+
+
+
+  // val syncSerDat = ShiftRegister( asyncSerDat, 2 )
+  val syncSerDat = ShiftRegister( asyncSerDat, 2 )
+
+}
+
+
 
 trait CDRInAxis{ this: CDRInBase =>