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16bit fsmc data; 16*2 reg, 100us

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RuigeLee
2023-09-08 16:37:31 +08:00
parent 145db92202
commit bf835014bc
4 changed files with 160 additions and 107 deletions
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190
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -123,73 +123,133 @@ class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDownIO extends Bundle{
val addrr = Input(UInt(10.W))
val addrw = Input(UInt(9.W))
val dataw = Input( UInt(16.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
}
val io: MirrorSRAMDownIO = IO(new MirrorSRAMDownIO)
setInline("MirrorSRAMDown.v",
"""
| module MirrorSRAMDown(
| input [15:0] dataw,
| input [8:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [9:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 addrr[0] ? ram[addrr[9:1]][15:8] : ram[addrr[9:1]][7:0];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
class MirrorSRAMUpIO extends Bundle{
val addrr = Input(UInt(9.W))
val addrw = Input(UInt(10.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(16.W) )
val enw = Input(Bool())
val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
}
val io: MirrorSRAMUpIO = IO(new MirrorSRAMUpIO)
setInline("MirrorSRAMUp.v",
"""
| module MirrorSRAMUp(
| input [7:0] dataw,
| input [9:0] addrw,
| input enw,
|
| output [15:0] datar,
| input [8:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [15:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| if( addrw[0] ) begin
| ram[addrw[9:1]] <= #1 { dataw, ram[addrw[9:1]][7:0] };
| end else begin
| ram[addrw[9:1]] <= #1 { ram[addrw[9:1]][15:8], dataw };
| end
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
// class MirrorSRAMIO extends Bundle{
// val datar = Output(UInt(8.W))
// val dataw = Input(UInt(8.W))
// val clock = Input(Bool())
// val reset = Input(Bool())
// val we = Input(Bool())
// val addrr = Input(UInt(11.W))
// val addrw = Input(UInt(11.W))
// }
// class MirrorSRAM extends BlackBox with HasBlackBoxInline {
// val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
// setInline("microSRAM.v",
// """
// | module MirrorSRAM(
// | output [7:0] datar,
// | input [7:0] dataw,
// |
// | input clock,
// | input reset,
// |
// | input we,
// |
// | input [11:0] addrw,
// | input [11:0] addrr
// |
// | );
// |
// | wire [31:0] dout;
// | assign datar = dout[7:0];
// |
// |
// |SDPB bram_sdpb_0 (
// | .DO({dout[31:8],dout[7:0]}),
// | .CLKA(clock),
// | .CEA(we),
// | .RESETA(reset),
// | .CLKB(clock),
// | .CEB(1'b1),
// | .RESETB(reset),
// | .OCE(1'b1),
// | .BLKSELA(3'b0),
// | .BLKSELB(3'b0),
// | .ADA({addrw,3'b0}),
// | .DI({24'b0, dataw}),
// | .ADB({addrr,3'b0})
// | );
// | defparam bram_sdpb_0.BIT_WIDTH_0 = 8;
// | defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
// | defparam bram_sdpb_0.RESET_MODE = "SYNC";
// |
// |endmodule
// """.stripMargin)
// }