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16bit fsmc data; 16*2 reg, 100us

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RuigeLee
2023-09-08 16:37:31 +08:00
parent 145db92202
commit bf835014bc
4 changed files with 160 additions and 107 deletions
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2
src/main/scala/backBoard/LocalRegisters.scala
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@@ -11,7 +11,7 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
withClockAndReset( io.ides_pclk.asClock, io.reset ){
// val upReg = Reg(Vec(32, UInt(8.W)))
val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
val upReg = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
upRegWire := upReg
out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
oe := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )