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16bit fsmc data; 16*2 reg, 100us

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This commit is contained in:
RuigeLee
2023-09-08 16:37:31 +08:00
parent 145db92202
commit bf835014bc
4 changed files with 160 additions and 107 deletions
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56
src/main/scala/backBoard/BackBoardMst.scala
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@@ -8,9 +8,9 @@ import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
val addr = Input(UInt(13.W))
val dataIn = Input(UInt(8.W))
val dataOut = Output(UInt(8.W))
val addr = Input(UInt(11.W))
val dataIn = Input(UInt(16.W))
val dataOut = Output(UInt(16.W))
val dataOEn = Output(Bool())
val cen = Input(Bool())
val oen = Input(Bool())
@@ -38,10 +38,10 @@ class BackBoardMstBase extends RawModule{
val lvdsMst = Module(new Lvds_Bus_Master)
val mirrorDown = Module(new MirrorSRAM(8, 2048))
val mirrorUp = Module(new MirrorSRAM(8, 2048))
val mirrorDown = Module(new MirrorSRAMDown())
val mirrorUp = Module(new MirrorSRAMUp())
val status = Wire(UInt(8.W))
val status = Wire(UInt(16.W))
val slvNum = Wire(UInt(5.W))
@@ -59,7 +59,7 @@ class BackBoardMstBase extends RawModule{
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val statusReg = RegInit(0.U(8.W)); status := statusReg
val statusReg = RegInit(0.U(16.W)); status := statusReg
val slvNumReg = RegInit(1.U(5.W)); slvNum := slvNumReg
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
@@ -71,33 +71,35 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
io.FSMC.dataOEn := io.FSMC.oen
val isWriteSRAM = ~fsmcAddrSync.extract(10) & fsmcAddrSync.extract(9)
val isReadSRAM = ~fsmcAddrSync.extract(10) & ~fsmcAddrSync.extract(9)
val isAccessReg = fsmcAddrSync.extract(10)
val activeAddr = fsmcAddrSync(8,0)
val regOut = Wire(UInt(16.W))
mirrorDown.io.enw := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & fsmcAddrSync.extract(11) & (~fsmcWEnSync) )
mirrorDown.io.addrw := fsmcAddrSync(10,0)
mirrorDown.io.dataw := fsmcdataInSync
mirrorDown.io.enw := (~fsmcCEnSync & isWriteSRAM & (~fsmcWEnSync) )
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := fsmcdataInSync
mirrorUp.io.enr := (~fsmcCEnSync & ~fsmcAddrSync.extract(12) & ~fsmcAddrSync.extract(11) & (~fsmcOEnSync) )
mirrorUp.io.addrr := fsmcAddrSync(10,0)
val regOut = Wire(UInt(8.W))
mirrorUp.io.enr := (~fsmcCEnSync & isReadSRAM & (~fsmcOEnSync) )
mirrorUp.io.addrr := activeAddr
io.FSMC.dataOut := Mux( fsmcAddrSync.extract(12), regOut, mirrorUp.io.datar)
io.FSMC.dataOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
regOut := Mux1H(Seq(
(fsmcAddrSync(10,0) === 0.U) -> status,
(fsmcAddrSync(10,0) === 1.U) -> slvNum,
( activeAddr === 0.U) -> status,
( activeAddr === 1.U) -> slvNum,
))
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 0.U) ){
when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
statusReg := fsmcdataInSync
}
when( (~fsmcCEnSync & fsmcAddrSync.extract(12) & (~fsmcWEnSync) ) & (fsmcAddrSync(10,0) === 1.U) ){
when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){
slvNumReg := fsmcdataInSync
}
@@ -128,7 +130,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
stateCur_wire := stateCur
val ( _, trigger ) = Counter(Range( 0,2000) )
val ( _, trigger ) = Counter(Range( 0,1000) )
trigger_wire := trigger
val isSync = RegInit(false.B)
@@ -165,7 +167,7 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
frame_info_update_en := true.B
slave_type_num := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b100".U(3.W), slvNum ) )
slave_data_length := (8/8*4*8-1).U
slave_data_length := ((8/8)*16-1).U
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -196,8 +198,8 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
val addrr = RegInit(0.U(11.W))
val addrw = RegInit(0.U(11.W))
val addrr = RegInit(0.U(10.W))
val addrw = RegInit(0.U(10.W))
when( trigger_wire ){
addrw := 0.U
@@ -219,8 +221,6 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ~isSync
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw
}