解耦rx/txlength，txcrc，后面应该整合tilelink模块，统一dma与mac
This commit is contained in:
RuigeLee
166
src/main/scala/Switch/DMA.scala
Normal file
166
src/main/scala/Switch/DMA.scala
Normal file
@@ -0,0 +1,166 @@
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package Switch
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
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class MacTileLinkMasterIO extends Bundle{
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val A = Decoupled(new TLBundleA(edgeOut.bundle))
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val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
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}
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class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{
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val dmaMst = new MacTileLinkMasterIO
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val triTx = Input(Bool())
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val triRx = Output(Bool())
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val r_TxPtr = Input(UInt(32.W))
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val r_RxPtr = Input(UInt(32.W))
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val r_TxLen = Input(UInt(16.W))
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val r_RxLen = Output(UInt(16.W))
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val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle))
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val txDeq = Vec(chn, new Transmit_Bundle)
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}
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val io: SwitchMuxIO = IO(new SwitchMuxIO)
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val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D)
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val rxBuff = Module(new RxBuff)
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rxBuff.io.enq <> io.rxEnq(0)
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val txBuff = Module(new TxBuff)
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txBuff.io.deq <> io.txDeq(0)
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def stateIdle = 0.U
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def stateRx = 1.U
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def stateTx = 2.U
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val stateNxt = Wire(UInt(2.W))
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val stateCur = RegNext(stateNxt, stateIdle)
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val stateDMA = RegInit(0.U(2.W))
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val dmaAValid = RegInit(false.B)
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val dmaABits = Reg(new TLBundleA(edgeOut.bundle))
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val dmaAddress = Reg( UInt(32.W) )
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}
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trait DMAMstFSM{ this: DMAMstBase =>
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stateNxt :=
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Mux1H(Seq(
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( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ),
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( stateCur === stateRx ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
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( stateCur === stateTx ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
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))
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when( stateNxt =/= stateIdle && stateCur === stateIdle ){
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stateDMA := 1.U
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} .elsewhen( io.dmaMst.A.fire ){
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stateDMA := 2.U
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} .elsewhen( io.dmaMst.D.fire & isLastD ){
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when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
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stateDMA := 0.U
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} .elsewhen( stateCur === stateRx & rxBuff.io.deq.req.valid ){
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stateDMA := 0.U
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} .otherwise{
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stateDMA := 1.U
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}
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}
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}
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trait DMAMstTileLink{ this: DMAMstBase =>
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when( stateCur === stateIdle & stateNxt === stateTx ){
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dmaAddress := io.r_TxPtr
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} .elsewhen( stateCur === stateIdle & stateNxt === stateRx ){
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dmaAddress := io.r_RxPtr
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} .elsewhen( io.dmaMst.A.fire ){
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dmaAddress := dmaAddress + 1.U
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}
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rxBuff.io.deq.req.ready := io.dmaMst.A.fire & (stateCur === stateRx)
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assert( ~(rxBuff.io.deq.req.ready & ~rxBuff.io.deq.req.valid) )
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rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
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when( io.dmaMst.A.fire ){
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dmaAValid := false.B
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}.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){
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dmaAValid := true.B
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dmaABits :=
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edgeOut.Get(
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fromSource = 0.U,
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toAddress = dmaAddress,
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lgSize = log2Ceil(8/8).U,
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)._2
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} .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) {
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dmaAValid := true.B
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dmaABits :=
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edgeOut.Put(
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fromSource = 0.U,
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toAddress = dmaAddress,
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lgSize = log2Ceil(8/8).U,
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data = rxBuff.io.deq.req.bits.data,
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mask = "b1".U,
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)._2
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}
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io.dmaMst.A.valid := dmaAValid
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io.dmaMst.A.bits := dmaABits
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io.dmaMst.D.ready :=
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Mux1H(Seq(
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( stateCur === stateRx ) -> true.B,
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( stateCur === stateTx ) -> txBuff.io.enq.req.ready,
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))
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}
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trait DMAMstBuff{ this: DMAMstBase =>
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val rxLength = RegInit(0.U)
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when( rxBuff.io.deq.req.fire ){
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when( rxBuff.io.deq.req.bits.isStart ){
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rxLength := 0.U
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} .otherwise{
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rxLength := rxLength + 1.U
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}
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}
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io.triRx := rxBuff.io.deq.ctrl.fire
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io.r_RxLen := RegEnable( rxLength, rxBuff.io.deq.ctrl.fire )
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rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
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txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx
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txBuff.io.enq.req.bits.data := io.dmaMst.D.bits.data
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txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr
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txBuff.io.enq.req.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen)
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txBuff.io.enq.resp.ready := true.B
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}
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class DMAMst(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMstBase(edgeOut)
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with DMAMstFSM
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with DMAMstTileLink
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with DMAMstBuff
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@@ -3,8 +3,10 @@ package Switch
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import chisel3._
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import chisel3.util._
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import MAC._
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class Receive_Enq_Ctrl_Bundle extends Bundle{
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val LatchedRxLength = UInt(16.W)
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// val LatchedRxLength = UInt(16.W)
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val RxStatusInLatched = UInt(9.W)
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}
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@@ -13,13 +15,13 @@ class Receive_Deq_Ctrl_Bundle extends Receive_Enq_Ctrl_Bundle{
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}
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class Receive_Enq_Bundle extends Bundle{
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val data = Decoupled(UInt(8.W))
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val req = Decoupled(new Mac_Stream_Bundle)
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val ctrl = Decoupled(new Receive_Enq_Ctrl_Bundle)
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}
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class Receive_Deq_Bundle extends Bundle{
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val data = Decoupled(UInt(8.W))
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val req = Decoupled(new Mac_Stream_Bundle)
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val ctrl = Decoupled(new Receive_Deq_Ctrl_Bundle)
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val header = Decoupled(Vec( 20, UInt(8.W) ) )
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}
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@@ -43,7 +45,7 @@ class RxBuffBase extends Module{
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val isDeqPo = ~isEnqPi
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val buff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(8.W), 2048 )) }
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val buff = for( i <- 0 until 2 ) yield { Module(new Queue( new Mac_Stream_Bundle, 2048 )) }
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val info = for( i <- 0 until 2 ) yield { Reg(new Receive_Enq_Ctrl_Bundle) }
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// dontTouch(buff(0).io.enq)
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// dontTouch(info(0))
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@@ -66,13 +68,13 @@ trait RxBuffEnq{ this: RxBuffBase =>
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buff(0).io.enq.valid := isEnqPi & io.enq.data.valid
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buff(0).io.enq.bits := io.enq.data.bits
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buff(0).io.enq.valid := isEnqPi & io.enq.req.valid
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buff(0).io.enq.bits := io.enq.req.bits
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buff(1).io.enq.valid := isEnqPo & io.enq.data.valid
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buff(1).io.enq.bits := io.enq.data.bits
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buff(1).io.enq.valid := isEnqPo & io.enq.req.valid
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buff(1).io.enq.bits := io.enq.req.bits
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io.enq.data.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
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io.enq.req.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
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io.enq.ctrl.ready := true.B
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when( io.enq.ctrl.fire ){
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@@ -88,13 +90,13 @@ trait RxBuffEnq{ this: RxBuffBase =>
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when( io.enq.ctrl.fire ){
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recCnt := 0.U
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} .elsewhen( io.enq.data.fire ){
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} .elsewhen( io.enq.req.fire ){
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when( recCnt < 20.U ){
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recCnt := recCnt + 1.U
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when( isEnqPi ){
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header(0)(recCnt) := io.enq.data.bits
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header(0)(recCnt) := io.enq.req.bits.data
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} .elsewhen( isEnqPo ){
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header(1)(recCnt) := io.enq.data.bits
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header(1)(recCnt) := io.enq.req.bits.data
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} .otherwise{
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assert(false.B, "Assert Failed, Rx Under Run")
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}
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@@ -110,7 +112,7 @@ trait RxBuffDeq{ this: RxBuffBase =>
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when( io.deq.header.fire ){
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when( isDeqPi ) { hValid(0) := false.B }
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when( isDeqPo ) { hValid(1) := false.B }
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} .elsewhen( io.enq.data.fire & recCnt === 20.U ){
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} .elsewhen( io.enq.req.fire & recCnt === 20.U ){
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when( isEnqPi ) { hValid(0) := true.B }
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when( isEnqPo ) { hValid(1) := true.B }
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}
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@@ -127,7 +129,7 @@ trait RxBuffDeq{ this: RxBuffBase =>
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when( isDeqPi ){
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io.deq.data <> buff(0).io.deq
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io.deq.req <> buff(0).io.deq
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buff(1).io.deq.ready := false.B
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io.deq.header.valid := hValid(0)
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@@ -137,7 +139,7 @@ trait RxBuffDeq{ this: RxBuffBase =>
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io.deq.ctrl.bits := info(0)
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} .otherwise{
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assert( isDeqPo )
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io.deq.data <> buff(1).io.deq
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io.deq.req <> buff(1).io.deq
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buff(0).io.deq.ready := false.B
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io.deq.header.valid := hValid(1)
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@@ -56,20 +56,20 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
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outer.ethReg.module.io.asyncReset := io.asyncReset
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outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
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val switchMux = Module(new SwitchMux(dma_edge))
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val dmaMst = Module(new DMAMst(dma_edge))
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switchMux.io.rxEnq(0) <> mac(0).io.rxEnq
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switchMux.io.txDeq(0) <> mac(0).io.txDeq
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dmaMst.io.rxEnq(0) <> mac(0).io.rxEnq
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dmaMst.io.txDeq(0) <> mac(0).io.txDeq
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switchMux.io.triTx := outer.ethReg.module.io.triTx
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outer.ethReg.module.io.triRx := switchMux.io.triRx
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dmaMst.io.triTx := outer.ethReg.module.io.triTx
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outer.ethReg.module.io.triRx := dmaMst.io.triRx
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switchMux.io.r_TxPtr := outer.ethReg.module.io.r_TxPtr
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switchMux.io.r_RxPtr := outer.ethReg.module.io.r_RxPtr
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switchMux.io.r_TxLen := outer.ethReg.module.io.r_TxLen
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outer.ethReg.module.io.r_RxLen := switchMux.io.r_RxLen
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dmaMst.io.r_TxPtr := outer.ethReg.module.io.r_TxPtr
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dmaMst.io.r_RxPtr := outer.ethReg.module.io.r_RxPtr
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dmaMst.io.r_TxLen := outer.ethReg.module.io.r_TxLen
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outer.ethReg.module.io.r_RxLen := dmaMst.io.r_RxLen
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@@ -82,12 +82,12 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
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switchMux.io.dmaMst.D.bits := dma_bus.d.bits
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switchMux.io.dmaMst.D.valid := dma_bus.d.valid
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dma_bus.d.ready := switchMux.io.dmaMst.D.ready
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dma_bus.a.valid := switchMux.io.dmaMst.A.valid
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dma_bus.a.bits := switchMux.io.dmaMst.A.bits
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switchMux.io.dmaMst.A.ready := dma_bus.a.ready
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dmaMst.io.dmaMst.D.bits := dma_bus.d.bits
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dmaMst.io.dmaMst.D.valid := dma_bus.d.valid
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dma_bus.d.ready := dmaMst.io.dmaMst.D.ready
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dma_bus.a.valid := dmaMst.io.dmaMst.A.valid
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dma_bus.a.bits := dmaMst.io.dmaMst.A.bits
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dmaMst.io.dmaMst.A.ready := dma_bus.a.ready
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@@ -11,7 +11,7 @@ import freechips.rocketchip.tilelink._
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class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
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abstract class SwitchMuxBase(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
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class MacTileLinkMasterIO extends Bundle{
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val A = Decoupled(new TLBundleA(edgeOut.bundle))
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@@ -49,47 +49,44 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
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val stateNxt = Wire(UInt(2.W))
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val stateCur = RegNext(stateNxt, stateIdle)
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val stateDMA = RegInit(0.U(2.W))
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when( stateNxt =/= stateIdle && stateCur === stateIdle ){
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stateDMA := 1.U
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} .elsewhen( io.dmaMst.A.fire ){
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stateDMA := 2.U
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} .elsewhen( io.dmaMst.D.fire & isLastD ){
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when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
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stateDMA := 0.U
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} .elsewhen( stateCur === stateRx & rxBuff.io.deq.data.valid ){
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stateDMA := 0.U
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} .otherwise{
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stateDMA := 1.U
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}
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}
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stateNxt :=
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Mux1H(Seq(
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( stateCur === stateIdle ) -> Mux( rxBuff.io.deq.header.fire, stateRx, Mux( txBuff.io.enq.req.fire, stateTx, stateIdle ) ),
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( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ),
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( stateCur === stateRx ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
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( stateCur === stateTx ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
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))
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def PerPacketCrcEn = true.B
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io.triRx := rxBuff.io.deq.ctrl.fire
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io.r_RxLen := RegEnable( rxBuff.io.deq.ctrl.bits.LatchedRxLength, rxBuff.io.deq.ctrl.fire )
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rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
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val txReqValid = RegInit(false.B)
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when( txBuff.io.enq.req.fire ){
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txReqValid := false.B
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} .elsewhen( io.triTx & io.r_TxLen > 32.U ){
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txReqValid := true.B
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}
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txBuff.io.enq.req.valid := txReqValid && stateCur === stateIdle
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txBuff.io.enq.req.bits.txLength := io.r_TxLen
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txBuff.io.enq.req.bits.PerPacketCrcEn := PerPacketCrcEn
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txBuff.io.enq.resp.ready := true.B
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val dmaTxAValid = RegInit(false.B)
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val dmaTxABits = Reg(new TLBundleA(edgeOut.bundle))
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val dmaAValid = RegInit(false.B)
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val dmaABits = Reg(new TLBundleA(edgeOut.bundle))
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val dmaAddress = Reg( UInt(32.W) )
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@@ -105,39 +102,21 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
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rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx)
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assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) )
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rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) && ~txReqValid & stateCur === stateIdle
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rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
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when( io.dmaMst.A.fire ){
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dmaTxAValid := false.B
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} .elsewhen( txBuff.io.enq.req.fire ){
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dmaTxAValid := true.B
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dmaTxABits :=
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edgeOut.Get(
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fromSource = 0.U,
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toAddress = io.r_TxPtr,
|
||||
lgSize = log2Ceil(8/8).U,
|
||||
)._2
|
||||
} .elsewhen( stateCur === stateTx & io.dmaMst.D.fire & isLastD & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
|
||||
dmaTxAValid := true.B
|
||||
dmaTxABits :=
|
||||
dmaAValid := false.B
|
||||
}.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){
|
||||
dmaAValid := true.B
|
||||
dmaABits :=
|
||||
edgeOut.Get(
|
||||
fromSource = 0.U,
|
||||
toAddress = dmaAddress,
|
||||
lgSize = log2Ceil(8/8).U,
|
||||
)._2
|
||||
} .elsewhen( rxBuff.io.deq.header.fire ) {
|
||||
dmaTxAValid := true.B
|
||||
dmaTxABits :=
|
||||
edgeOut.Put(
|
||||
fromSource = 0.U,
|
||||
toAddress = io.r_RxPtr,
|
||||
lgSize = log2Ceil(8/8).U,
|
||||
data = rxBuff.io.deq.data.bits,
|
||||
mask = "b1".U,
|
||||
)._2
|
||||
} .elsewhen( stateCur === stateRx & io.dmaMst.D.fire & isLastD & rxBuff.io.deq.data.valid ) {
|
||||
dmaTxAValid := true.B
|
||||
dmaTxABits :=
|
||||
} .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) {
|
||||
dmaAValid := true.B
|
||||
dmaABits :=
|
||||
edgeOut.Put(
|
||||
fromSource = 0.U,
|
||||
toAddress = dmaAddress,
|
||||
@@ -148,19 +127,21 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
|
||||
}
|
||||
|
||||
|
||||
io.dmaMst.A.valid := dmaTxAValid
|
||||
io.dmaMst.A.bits := dmaTxABits
|
||||
io.dmaMst.A.valid := dmaAValid
|
||||
io.dmaMst.A.bits := dmaABits
|
||||
|
||||
|
||||
|
||||
txBuff.io.enq.data.valid := io.dmaMst.D.valid & stateCur === stateTx
|
||||
txBuff.io.enq.data.bits := io.dmaMst.D.bits.data
|
||||
txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx
|
||||
txBuff.io.enq.req.bits.data := io.dmaMst.D.bits.data
|
||||
txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr
|
||||
txBuff.io.enq.req.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen)
|
||||
|
||||
|
||||
io.dmaMst.D.ready :=
|
||||
Mux1H(Seq(
|
||||
( stateCur === stateRx ) -> true.B,
|
||||
( stateCur === stateTx ) -> txBuff.io.enq.data.ready,
|
||||
( stateCur === stateTx ) -> txBuff.io.enq.req.ready,
|
||||
))
|
||||
|
||||
|
||||
@@ -168,3 +149,11 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
trait SwitchMuxDMATx{ this: SwitchMuxBase =>
|
||||
|
||||
}
|
||||
|
||||
class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchMuxBase(TLEdgeOut)
|
||||
with SwitchMuxDMATx
|
||||
@@ -3,14 +3,14 @@ package Switch
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
import MAC._
|
||||
|
||||
|
||||
|
||||
|
||||
class Transmit_Req_Bundle extends Bundle{
|
||||
val txLength = UInt(16.W)
|
||||
val PerPacketCrcEn = Bool()
|
||||
}
|
||||
// class Transmit_Req_Bundle extends Bundle{
|
||||
// // val txLength = UInt(16.W)
|
||||
// val PerPacketCrcEn = Bool()
|
||||
// }
|
||||
|
||||
class Transmit_Resp_Bundle extends Bundle{
|
||||
val RetryLimit = Bool()
|
||||
@@ -22,8 +22,7 @@ class Transmit_Resp_Bundle extends Bundle{
|
||||
}
|
||||
|
||||
class Transmit_Bundle extends Bundle{
|
||||
val data = Decoupled(UInt(8.W))
|
||||
val req = Decoupled(new Transmit_Req_Bundle)
|
||||
val req = Decoupled(new Mac_Stream_Bundle)
|
||||
val resp = Flipped(Decoupled(new Transmit_Resp_Bundle))
|
||||
}
|
||||
|
||||
@@ -36,63 +35,36 @@ class TxBuffIO extends Bundle{
|
||||
abstract class TxBuffBase extends Module{
|
||||
val io: TxBuffIO = IO(new TxBuffIO)
|
||||
|
||||
|
||||
|
||||
val buff = Module(new Queue( UInt(8.W), 2048 ))
|
||||
val reqInfo = Reg(new Transmit_Req_Bundle)
|
||||
val respInfo = Reg(new Transmit_Resp_Bundle)
|
||||
val buff = Module(new Queue( new Mac_Stream_Bundle, 2048 ))
|
||||
val enqCnt = Reg(UInt(16.W))
|
||||
val deqReqValid = RegInit(false.B)
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait TxBuffEnq{ this: TxBuffBase =>
|
||||
io.enq.data <> buff.io.enq
|
||||
io.enq.req <> buff.io.enq
|
||||
|
||||
|
||||
when( io.enq.req.fire ){
|
||||
enqCnt := 0.U
|
||||
reqInfo := io.enq.req.bits
|
||||
} .elsewhen( io.enq.data.fire ){
|
||||
enqCnt := enqCnt + 1.U
|
||||
}
|
||||
when( io.enq.req.bits.isStart ) {
|
||||
enqCnt := 0.U
|
||||
} .elsewhen( io.enq.req.bits.isLast ){
|
||||
|
||||
|
||||
io.enq.req.ready := ~buff.io.deq.valid
|
||||
|
||||
|
||||
when( io.deq.req.fire ){
|
||||
deqReqValid := false.B
|
||||
} .elsewhen( io.enq.data.fire && enqCnt === 32.U ) {
|
||||
deqReqValid := true.B
|
||||
}
|
||||
} .otherwise{
|
||||
enqCnt := enqCnt + 1.U
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
trait TxBuffDeq{ this: TxBuffBase =>
|
||||
val isBusy = RegInit(false.B)
|
||||
|
||||
when( io.deq.req.fire ){
|
||||
assert( ~isBusy )
|
||||
isBusy := true.B
|
||||
} .elsewhen(io.deq.resp.fire){
|
||||
assert( isBusy )
|
||||
isBusy := false.B
|
||||
}
|
||||
|
||||
io.deq.resp <> io.enq.resp
|
||||
|
||||
io.deq.req.valid := deqReqValid
|
||||
io.deq.req.bits := reqInfo
|
||||
|
||||
io.deq.data.bits := buff.io.deq.bits
|
||||
io.deq.data.valid := buff.io.deq.valid & isBusy
|
||||
buff.io.deq.ready := io.deq.data.ready & isBusy
|
||||
|
||||
io.deq.req.bits := buff.io.deq.bits
|
||||
io.deq.req.valid := buff.io.deq.valid
|
||||
buff.io.deq.ready := io.deq.req.ready
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -516,7 +516,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
|
||||
val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
|
||||
|
||||
|
||||
val txReq_ToAsync = Wire(new AsyncBundle(new TxFifo_Stream_Bundle))
|
||||
val txReq_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
|
||||
txReq_ToAsync <> ToAsyncBundle( wishbone.io.txReq )
|
||||
withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset) {
|
||||
macTileLinkTx.io.txReq <> FromAsyncBundle( txReq_ToAsync )
|
||||
@@ -567,7 +567,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
|
||||
val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
|
||||
|
||||
|
||||
val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
|
||||
val req_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
|
||||
val resp_ToAsync = Wire(new AsyncBundle(Bool()))
|
||||
val fateRxRespPort = Wire( Flipped(Decoupled(Bool())) )
|
||||
fateRxRespPort.ready := true.B
|
||||
@@ -586,7 +586,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
|
||||
|
||||
|
||||
|
||||
wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
|
||||
// wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
|
||||
wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
|
||||
|
||||
|
||||
@@ -608,7 +608,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
|
||||
macTileLinkRx.io.RxEndFrm := RxEndFrm
|
||||
|
||||
|
||||
macTileLinkRx.io.RxLength := RxByteCnt
|
||||
// macTileLinkRx.io.RxLength := RxByteCnt
|
||||
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
|
||||
macTileLinkRx.io.RxStatusIn := Cat(false.B, false.B, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)
|
||||
|
||||
|
||||
@@ -4,8 +4,9 @@ import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
|
||||
class RxFifo_Stream_Bundle extends Bundle{
|
||||
class Mac_Stream_Bundle extends Bundle{
|
||||
val data = UInt(8.W)
|
||||
val isStart = Bool()
|
||||
val isLast = Bool()
|
||||
}
|
||||
|
||||
@@ -13,12 +14,12 @@ class RxFifo_Stream_Bundle extends Bundle{
|
||||
|
||||
class MacTileLinkRxIO extends Bundle{
|
||||
|
||||
val rxReq = Decoupled(new RxFifo_Stream_Bundle)
|
||||
val rxReq = Decoupled(new Mac_Stream_Bundle)
|
||||
|
||||
val LatchedRxLength = Output(UInt(16.W))
|
||||
// val LatchedRxLength = Output(UInt(16.W))
|
||||
val RxStatusInLatched = Output( UInt(9.W) )
|
||||
|
||||
val RxLength = Input(UInt(16.W))
|
||||
// val RxLength = Input(UInt(16.W))
|
||||
val LoadRxStatus = Input(Bool())
|
||||
val RxStatusIn = Input(UInt(9.W))
|
||||
|
||||
@@ -40,7 +41,7 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
|
||||
|
||||
val ShiftWillEnd = RegInit(false.B)
|
||||
|
||||
val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
|
||||
// val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
|
||||
val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
|
||||
|
||||
// val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
|
||||
@@ -70,9 +71,10 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
|
||||
}
|
||||
|
||||
|
||||
val rxFifo = Module(new Queue(new RxFifo_Stream_Bundle, 4))
|
||||
val rxFifo = Module(new Queue(new Mac_Stream_Bundle, 4))
|
||||
rxFifo.io.enq.valid := SetWriteRxDataToFifo
|
||||
rxFifo.io.enq.bits.data := io.RxData
|
||||
rxFifo.io.enq.bits.isStart := io.RxStartFrm
|
||||
rxFifo.io.enq.bits.isLast := io.RxEndFrm
|
||||
assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )
|
||||
|
||||
|
||||
@@ -4,16 +4,12 @@ import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
|
||||
class TxFifo_Stream_Bundle extends Bundle{
|
||||
val data = UInt(8.W)
|
||||
val isStart = Bool()
|
||||
val isLast = Bool()
|
||||
}
|
||||
|
||||
|
||||
|
||||
class MacTileLinkTxIO extends Bundle{
|
||||
|
||||
val txReq = Flipped(Decoupled(new TxFifo_Stream_Bundle))
|
||||
val txReq = Flipped(Decoupled(new Mac_Stream_Bundle))
|
||||
// val txResp = Decoupled()
|
||||
|
||||
|
||||
@@ -63,12 +59,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
|
||||
TxStartFrm := false.B
|
||||
}
|
||||
|
||||
// // Indication of the last word
|
||||
// when( (TxEndFrm | io.TxAbort) & Flop ){
|
||||
// LastWord := false.B
|
||||
// } .elsewhen( io.txReq.fire ){
|
||||
// LastWord := io.txReq.bits.isLast
|
||||
// }
|
||||
|
||||
|
||||
// Tx end frame generation
|
||||
when(Flop & TxEndFrm | io.TxAbort){
|
||||
|
||||
@@ -21,16 +21,16 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
val r_RxEn = Input(Bool()) // Receive enable
|
||||
|
||||
val rxReq = Flipped(Decoupled(new RxFifo_Stream_Bundle))
|
||||
val rxReq = Flipped(Decoupled(new Mac_Stream_Bundle))
|
||||
val rxResp = Decoupled(new Bool())
|
||||
|
||||
val LatchedRxLength_rxclk = Input(UInt(16.W))
|
||||
// val LatchedRxLength_rxclk = Input(UInt(16.W))
|
||||
val RxStatusInLatched_rxclk = Input(UInt(9.W))
|
||||
val RxReady = Output(Bool())
|
||||
|
||||
|
||||
|
||||
val txReq = Decoupled(new TxFifo_Stream_Bundle)
|
||||
val txReq = Decoupled(new Mac_Stream_Bundle)
|
||||
|
||||
// val TxEndFrm_wb = Output(Bool())
|
||||
|
||||
@@ -70,7 +70,7 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
val rxBuffCtrlValid = RegInit(false.B)
|
||||
io.rxEnq.ctrl.valid := rxBuffCtrlValid
|
||||
io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse )
|
||||
// io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse )
|
||||
io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse )
|
||||
|
||||
|
||||
@@ -85,14 +85,14 @@ abstract class MacTileLinkBase() extends Module{
|
||||
// RxReady generation
|
||||
when(ShiftEndedSyncPluse ){
|
||||
RxReady := false.B
|
||||
} .elsewhen( io.r_RxEn & (io.rxEnq.data.ready) ){
|
||||
} .elsewhen( io.r_RxEn & (io.rxEnq.req.ready) ){
|
||||
RxReady := true.B
|
||||
}
|
||||
|
||||
|
||||
io.rxEnq.data.bits := io.rxReq.bits.data
|
||||
io.rxEnq.data.valid := io.rxReq.valid
|
||||
io.rxReq.ready := io.rxEnq.data.ready
|
||||
io.rxEnq.req.bits := io.rxReq.bits
|
||||
io.rxEnq.req.valid := io.rxReq.valid
|
||||
io.rxReq.ready := io.rxEnq.req.ready
|
||||
|
||||
val rxRespValid = RegInit(false.B)
|
||||
when( io.rxResp.fire ){
|
||||
@@ -103,7 +103,7 @@ abstract class MacTileLinkBase() extends Module{
|
||||
io.rxResp.valid := rxRespValid
|
||||
io.rxResp.bits := DontCare
|
||||
|
||||
assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" )
|
||||
assert( ~(io.rxEnq.req.valid & ~io.rxEnq.req.ready), "Assert Failed, rx overrun!" )
|
||||
|
||||
|
||||
|
||||
@@ -125,42 +125,40 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
|
||||
|
||||
val TxStartFrm_wb = RegInit(false.B)
|
||||
val TxEndFrm_wb = RegInit(false.B)//; io.TxEndFrm_wb := TxEndFrm_wb
|
||||
// val TxStartFrm_wb = RegInit(false.B)
|
||||
// val TxEndFrm_wb = RegInit(false.B)
|
||||
|
||||
val TxLength = RegInit(0.U(16.W))
|
||||
val LatchedTxLength = RegInit(0.U(16.W))
|
||||
// val TxLength = RegInit(0.U(16.W))
|
||||
|
||||
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
|
||||
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
|
||||
|
||||
|
||||
io.PerPacketCrcEn := RegEnable(io.txDeq.req.bits.PerPacketCrcEn, false.B, io.txDeq.req.fire)
|
||||
io.PerPacketCrcEn := false.B
|
||||
|
||||
when( io.txDeq.req.fire ){
|
||||
TxStartFrm_wb := true.B
|
||||
} .elsewhen(io.txReq.fire){
|
||||
TxStartFrm_wb := false.B
|
||||
}
|
||||
// when( io.txDeq.req.fire ){
|
||||
// TxStartFrm_wb := true.B
|
||||
// } .elsewhen(io.txReq.fire){
|
||||
// TxStartFrm_wb := false.B
|
||||
// }
|
||||
|
||||
|
||||
when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
|
||||
TxEndFrm_wb := true.B
|
||||
} .elsewhen(txDonePulse | txAbortPulse){
|
||||
TxEndFrm_wb := false.B
|
||||
}
|
||||
// when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
|
||||
// TxEndFrm_wb := true.B
|
||||
// } .elsewhen(txDonePulse | txAbortPulse){
|
||||
// TxEndFrm_wb := false.B
|
||||
// }
|
||||
|
||||
when( io.txDeq.req.fire ){
|
||||
|
||||
TxLength := io.txDeq.req.bits.txLength
|
||||
LatchedTxLength := io.txDeq.req.bits.txLength
|
||||
} .elsewhen( io.txDeq.data.fire ){
|
||||
when( TxLength < 1.U ){
|
||||
TxLength := 0.U
|
||||
} .otherwise{
|
||||
TxLength := TxLength - 1.U // Length is subtracted at the data request
|
||||
}
|
||||
}
|
||||
// val TxLength = RegInit(0.U(16.W))
|
||||
// when( io.txDeq.req.fire ){
|
||||
// TxLength := io.txDeq.req.bits.txLength
|
||||
// } .elsewhen( io.txDeq.data.fire ){
|
||||
// when( TxLength < 1.U ){
|
||||
// TxLength := 0.U
|
||||
// } .otherwise{
|
||||
// TxLength := TxLength - 1.U // Length is subtracted at the data request
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
val txRespValid = RegInit(false.B)
|
||||
@@ -195,13 +193,13 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
|
||||
|
||||
io.txReq.bits.isLast := TxEndFrm_wb
|
||||
io.txReq.bits.data := io.txDeq.data.bits
|
||||
io.txReq.bits.isStart := TxStartFrm_wb
|
||||
io.txReq.valid := io.txDeq.data.valid
|
||||
io.txDeq.data.ready := io.txReq.ready
|
||||
// io.txReq.bits.isLast := TxEndFrm_wb
|
||||
|
||||
// io.txReq.bits.isStart := TxStartFrm_wb
|
||||
// io.txReq.valid := io.txDeq.data.valid
|
||||
// io.txDeq.data.ready := io.txReq.ready
|
||||
|
||||
io.txReq <> io.txDeq.req
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user