解耦rx/txlength，txcrc，后面应该整合tilelink模块，统一dma与mac

src/main/scala/Switch/DMA.scala

@@ -0,0 +1,166 @@
+package Switch
+
+import chisel3._
+import chisel3.util._
+
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+
+
+
+abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
+  class MacTileLinkMasterIO extends Bundle{
+    val A = Decoupled(new TLBundleA(edgeOut.bundle))
+    val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
+  }
+
+  class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{
+    val dmaMst = new MacTileLinkMasterIO
+
+    val triTx = Input(Bool())
+    val triRx = Output(Bool())
+    val r_TxPtr = Input(UInt(32.W))
+    val r_RxPtr = Input(UInt(32.W))
+    val r_TxLen = Input(UInt(16.W))
+    val r_RxLen = Output(UInt(16.W))
+
+    val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle))
+    val txDeq = Vec(chn, new Transmit_Bundle)
+
+  }
+
+  val io: SwitchMuxIO = IO(new SwitchMuxIO)
+  val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D)
+
+  val rxBuff = Module(new RxBuff)
+  rxBuff.io.enq <> io.rxEnq(0)
+
+
+  val txBuff = Module(new TxBuff)
+  txBuff.io.deq <> io.txDeq(0)
+
+  def stateIdle = 0.U
+  def stateRx   = 1.U
+  def stateTx   = 2.U
+
+  val stateNxt = Wire(UInt(2.W))
+  val stateCur = RegNext(stateNxt, stateIdle)
+  val stateDMA = RegInit(0.U(2.W))
+
+  val dmaAValid = RegInit(false.B)
+  val dmaABits  = Reg(new TLBundleA(edgeOut.bundle))
+  val dmaAddress = Reg( UInt(32.W) )
+}
+
+trait DMAMstFSM{ this: DMAMstBase =>
+
+  stateNxt := 
+    Mux1H(Seq(
+      ( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ),
+      ( stateCur === stateRx   ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
+      ( stateCur === stateTx   ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
+    ))
+
+
+  when( stateNxt =/= stateIdle && stateCur === stateIdle ){
+    stateDMA := 1.U
+  } .elsewhen( io.dmaMst.A.fire ){
+    stateDMA := 2.U
+  } .elsewhen( io.dmaMst.D.fire & isLastD ){
+    when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
+      stateDMA := 0.U
+    } .elsewhen( stateCur === stateRx & rxBuff.io.deq.req.valid  ){
+      stateDMA := 0.U
+    } .otherwise{
+      stateDMA := 1.U
+    }
+  }
+
+}
+
+
+trait DMAMstTileLink{ this: DMAMstBase =>
+
+
+
+
+
+  when( stateCur === stateIdle & stateNxt === stateTx ){
+    dmaAddress := io.r_TxPtr
+  } .elsewhen( stateCur === stateIdle & stateNxt === stateRx ){
+    dmaAddress := io.r_RxPtr
+  } .elsewhen( io.dmaMst.A.fire ){
+    dmaAddress := dmaAddress + 1.U
+  }
+
+  rxBuff.io.deq.req.ready := io.dmaMst.A.fire & (stateCur === stateRx)
+  assert( ~(rxBuff.io.deq.req.ready & ~rxBuff.io.deq.req.valid) )
+
+  rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
+
+  when( io.dmaMst.A.fire ){
+    dmaAValid := false.B
+  }.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){
+    dmaAValid := true.B
+    dmaABits :=
+      edgeOut.Get(
+        fromSource = 0.U,
+        toAddress = dmaAddress,
+        lgSize = log2Ceil(8/8).U,
+      )._2
+  } .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) {
+    dmaAValid := true.B
+    dmaABits :=
+      edgeOut.Put(
+        fromSource = 0.U,
+        toAddress = dmaAddress,
+        lgSize = log2Ceil(8/8).U,
+        data = rxBuff.io.deq.req.bits.data,
+        mask = "b1".U,
+      )._2
+  }
+
+
+  io.dmaMst.A.valid := dmaAValid
+  io.dmaMst.A.bits := dmaABits
+
+
+  io.dmaMst.D.ready := 
+    Mux1H(Seq(
+      ( stateCur === stateRx ) -> true.B,
+      ( stateCur === stateTx ) -> txBuff.io.enq.req.ready,
+    ))
+}
+
+trait DMAMstBuff{ this: DMAMstBase =>
+
+  val rxLength = RegInit(0.U)
+
+  when( rxBuff.io.deq.req.fire ){
+    when( rxBuff.io.deq.req.bits.isStart ){
+      rxLength := 0.U
+    } .otherwise{
+      rxLength := rxLength + 1.U
+    }
+  }
+
+  io.triRx := rxBuff.io.deq.ctrl.fire
+  io.r_RxLen := RegEnable( rxLength, rxBuff.io.deq.ctrl.fire )
+  rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
+
+
+  txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx
+  txBuff.io.enq.req.bits.data  := io.dmaMst.D.bits.data
+  txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr
+  txBuff.io.enq.req.bits.isLast  := dmaAddress === (io.r_TxPtr + io.r_TxLen)
+  txBuff.io.enq.resp.ready := true.B
+}
+
+
+class DMAMst(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMstBase(edgeOut)
+with DMAMstFSM
+with DMAMstTileLink
+with DMAMstBuff

src/main/scala/Switch/RxBuff.scala

@@ -3,8 +3,10 @@ package Switch
 import chisel3._
 import chisel3.util._
 
+import MAC._
+
 class Receive_Enq_Ctrl_Bundle extends Bundle{
-  val LatchedRxLength   = UInt(16.W)
+  // val LatchedRxLength   = UInt(16.W)
   val RxStatusInLatched = UInt(9.W)
 }
 
@@ -13,13 +15,13 @@ class Receive_Deq_Ctrl_Bundle extends Receive_Enq_Ctrl_Bundle{
 }
 
 class Receive_Enq_Bundle extends Bundle{
-  val data = Decoupled(UInt(8.W))
+  val req = Decoupled(new Mac_Stream_Bundle)
   val ctrl = Decoupled(new Receive_Enq_Ctrl_Bundle)
 }
 
 
 class Receive_Deq_Bundle extends Bundle{
-  val data = Decoupled(UInt(8.W))
+  val req = Decoupled(new Mac_Stream_Bundle)
   val ctrl = Decoupled(new Receive_Deq_Ctrl_Bundle)
   val header = Decoupled(Vec( 20, UInt(8.W) ) )
 }
@@ -43,7 +45,7 @@ class RxBuffBase extends Module{
   val isDeqPo = ~isEnqPi
 
 
-  val buff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(8.W), 2048 )) }
+  val buff = for( i <- 0 until 2 ) yield { Module(new Queue( new Mac_Stream_Bundle, 2048 )) }
   val info = for( i <- 0 until 2 ) yield { Reg(new Receive_Enq_Ctrl_Bundle) }
   // dontTouch(buff(0).io.enq)
   // dontTouch(info(0))
@@ -66,13 +68,13 @@ trait RxBuffEnq{ this: RxBuffBase =>
 
 
 
-  buff(0).io.enq.valid := isEnqPi & io.enq.data.valid
+  buff(0).io.enq.valid := isEnqPi & io.enq.req.valid
-  buff(0).io.enq.bits  := io.enq.data.bits
+  buff(0).io.enq.bits  := io.enq.req.bits
 
-  buff(1).io.enq.valid := isEnqPo & io.enq.data.valid
+  buff(1).io.enq.valid := isEnqPo & io.enq.req.valid
-  buff(1).io.enq.bits  := io.enq.data.bits
+  buff(1).io.enq.bits  := io.enq.req.bits
 
-  io.enq.data.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
+  io.enq.req.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
   io.enq.ctrl.ready := true.B
 
   when( io.enq.ctrl.fire ){
@@ -88,13 +90,13 @@ trait RxBuffEnq{ this: RxBuffBase =>
 
   when( io.enq.ctrl.fire ){
     recCnt := 0.U
-  } .elsewhen( io.enq.data.fire ){
+  } .elsewhen( io.enq.req.fire ){
     when( recCnt < 20.U ){
       recCnt := recCnt + 1.U
       when( isEnqPi ){
-        header(0)(recCnt) := io.enq.data.bits
+        header(0)(recCnt) := io.enq.req.bits.data
       } .elsewhen( isEnqPo ){
-        header(1)(recCnt) := io.enq.data.bits
+        header(1)(recCnt) := io.enq.req.bits.data
       } .otherwise{
         assert(false.B, "Assert Failed, Rx Under Run")
       }
@@ -110,7 +112,7 @@ trait RxBuffDeq{ this: RxBuffBase =>
   when( io.deq.header.fire ){
     when( isDeqPi ) { hValid(0) := false.B }
     when( isDeqPo ) { hValid(1) := false.B }
-  } .elsewhen( io.enq.data.fire & recCnt === 20.U ){
+  } .elsewhen( io.enq.req.fire & recCnt === 20.U ){
     when( isEnqPi ) { hValid(0) := true.B }
     when( isEnqPo ) { hValid(1) := true.B }
   }
@@ -127,7 +129,7 @@ trait RxBuffDeq{ this: RxBuffBase =>
 
 
   when( isDeqPi ){
-    io.deq.data <> buff(0).io.deq
+    io.deq.req <> buff(0).io.deq
     buff(1).io.deq.ready := false.B
 
     io.deq.header.valid := hValid(0)
@@ -137,7 +139,7 @@ trait RxBuffDeq{ this: RxBuffBase =>
     io.deq.ctrl.bits  := info(0)
   } .otherwise{
     assert( isDeqPo )
-    io.deq.data <> buff(1).io.deq
+    io.deq.req <> buff(1).io.deq
     buff(0).io.deq.ready := false.B
 
     io.deq.header.valid := hValid(1)

src/main/scala/Switch/Switch.scala

@@ -56,20 +56,20 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
   outer.ethReg.module.io.asyncReset := io.asyncReset
   outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
 
-  val switchMux = Module(new SwitchMux(dma_edge))
+  val dmaMst = Module(new DMAMst(dma_edge))
 
-  switchMux.io.rxEnq(0) <> mac(0).io.rxEnq
+  dmaMst.io.rxEnq(0) <> mac(0).io.rxEnq
-  switchMux.io.txDeq(0) <> mac(0).io.txDeq
+  dmaMst.io.txDeq(0) <> mac(0).io.txDeq
 
 
-  switchMux.io.triTx             := outer.ethReg.module.io.triTx
+  dmaMst.io.triTx             := outer.ethReg.module.io.triTx
-  outer.ethReg.module.io.triRx := switchMux.io.triRx
+  outer.ethReg.module.io.triRx := dmaMst.io.triRx
 
 
-  switchMux.io.r_TxPtr           := outer.ethReg.module.io.r_TxPtr
+  dmaMst.io.r_TxPtr           := outer.ethReg.module.io.r_TxPtr
-  switchMux.io.r_RxPtr           := outer.ethReg.module.io.r_RxPtr
+  dmaMst.io.r_RxPtr           := outer.ethReg.module.io.r_RxPtr
-  switchMux.io.r_TxLen           := outer.ethReg.module.io.r_TxLen
+  dmaMst.io.r_TxLen           := outer.ethReg.module.io.r_TxLen
-  outer.ethReg.module.io.r_RxLen := switchMux.io.r_RxLen
+  outer.ethReg.module.io.r_RxLen := dmaMst.io.r_RxLen
 
 
 
@@ -82,12 +82,12 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
 
 
 
-  switchMux.io.dmaMst.D.bits  := dma_bus.d.bits
+  dmaMst.io.dmaMst.D.bits  := dma_bus.d.bits
-  switchMux.io.dmaMst.D.valid := dma_bus.d.valid
+  dmaMst.io.dmaMst.D.valid := dma_bus.d.valid
-  dma_bus.d.ready := switchMux.io.dmaMst.D.ready
+  dma_bus.d.ready := dmaMst.io.dmaMst.D.ready
-  dma_bus.a.valid := switchMux.io.dmaMst.A.valid
+  dma_bus.a.valid := dmaMst.io.dmaMst.A.valid
-  dma_bus.a.bits  := switchMux.io.dmaMst.A.bits
+  dma_bus.a.bits  := dmaMst.io.dmaMst.A.bits
-  switchMux.io.dmaMst.A.ready := dma_bus.a.ready
+  dmaMst.io.dmaMst.A.ready := dma_bus.a.ready
 
 
 

src/main/scala/Switch/SwitchMux.scala.bk

@@ -11,7 +11,7 @@ import freechips.rocketchip.tilelink._
 
 
 
-class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
+abstract class SwitchMuxBase(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
 
   class MacTileLinkMasterIO extends Bundle{
     val A = Decoupled(new TLBundleA(edgeOut.bundle))
@@ -49,47 +49,44 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
 
   val stateNxt = Wire(UInt(2.W))
   val stateCur = RegNext(stateNxt, stateIdle)
+  val stateDMA = RegInit(0.U(2.W))
+
+  when( stateNxt =/= stateIdle && stateCur === stateIdle ){
+    stateDMA := 1.U
+  } .elsewhen( io.dmaMst.A.fire ){
+    stateDMA := 2.U
+  } .elsewhen( io.dmaMst.D.fire & isLastD ){
+    when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
+      stateDMA := 0.U
+    } .elsewhen( stateCur === stateRx & rxBuff.io.deq.data.valid  ){
+      stateDMA := 0.U
+    } .otherwise{
+      stateDMA := 1.U
+    }
+  }
+
+
 
   stateNxt := 
     Mux1H(Seq(
-      ( stateCur === stateIdle ) -> Mux( rxBuff.io.deq.header.fire, stateRx, Mux( txBuff.io.enq.req.fire, stateTx, stateIdle ) ),
+      ( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ),
       ( stateCur === stateRx   ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
       ( stateCur === stateTx   ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
     ))
 
-
-    def PerPacketCrcEn = true.B
-
-
-
   io.triRx := rxBuff.io.deq.ctrl.fire
   io.r_RxLen := RegEnable( rxBuff.io.deq.ctrl.bits.LatchedRxLength, rxBuff.io.deq.ctrl.fire )
   rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
 
 
-  val txReqValid = RegInit(false.B)
-
-  when( txBuff.io.enq.req.fire ){
-    txReqValid := false.B
-  } .elsewhen( io.triTx & io.r_TxLen > 32.U ){
-    txReqValid := true.B
-  }
-
-  txBuff.io.enq.req.valid := txReqValid && stateCur === stateIdle
-  txBuff.io.enq.req.bits.txLength := io.r_TxLen
-  txBuff.io.enq.req.bits.PerPacketCrcEn := PerPacketCrcEn
-
-
-
-
   txBuff.io.enq.resp.ready := true.B
 
 
 
 
 
-  val dmaTxAValid = RegInit(false.B)
+  val dmaAValid = RegInit(false.B)
-  val dmaTxABits  = Reg(new TLBundleA(edgeOut.bundle))
+  val dmaABits  = Reg(new TLBundleA(edgeOut.bundle))
 
 
   val dmaAddress = Reg( UInt(32.W) )
@@ -105,39 +102,21 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
   rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx)
   assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) )
 
-  rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) && ~txReqValid & stateCur === stateIdle
+  rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
 
   when( io.dmaMst.A.fire ){
-    dmaTxAValid := false.B
+    dmaAValid := false.B
-  } .elsewhen( txBuff.io.enq.req.fire ){
+  }.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){
-    dmaTxAValid := true.B
+    dmaAValid := true.B
-    dmaTxABits :=
+    dmaABits :=
-      edgeOut.Get(
-        fromSource = 0.U,
-        toAddress = io.r_TxPtr,
-        lgSize = log2Ceil(8/8).U,
-      )._2
-  } .elsewhen( stateCur === stateTx & io.dmaMst.D.fire & isLastD & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
-    dmaTxAValid := true.B
-    dmaTxABits :=
       edgeOut.Get(
         fromSource = 0.U,
         toAddress = dmaAddress,
         lgSize = log2Ceil(8/8).U,
       )._2
-  } .elsewhen( rxBuff.io.deq.header.fire ) {
+  } .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) {
-    dmaTxAValid := true.B
+    dmaAValid := true.B
-    dmaTxABits :=
+    dmaABits :=
-      edgeOut.Put(
-        fromSource = 0.U,
-        toAddress = io.r_RxPtr,
-        lgSize = log2Ceil(8/8).U,
-        data = rxBuff.io.deq.data.bits,
-        mask = "b1".U,
-      )._2
-  } .elsewhen( stateCur === stateRx & io.dmaMst.D.fire & isLastD & rxBuff.io.deq.data.valid ) {
-    dmaTxAValid := true.B
-    dmaTxABits :=
       edgeOut.Put(
         fromSource = 0.U,
         toAddress = dmaAddress,
@@ -148,19 +127,21 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
   }
 
 
-  io.dmaMst.A.valid := dmaTxAValid
+  io.dmaMst.A.valid := dmaAValid
-  io.dmaMst.A.bits := dmaTxABits
+  io.dmaMst.A.bits := dmaABits
 
 
 
-  txBuff.io.enq.data.valid := io.dmaMst.D.valid & stateCur === stateTx
+  txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx
-  txBuff.io.enq.data.bits  := io.dmaMst.D.bits.data
+  txBuff.io.enq.req.bits.data  := io.dmaMst.D.bits.data
+  txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr
+  txBuff.io.enq.req.bits.isLast  := dmaAddress === (io.r_TxPtr + io.r_TxLen)
 
 
   io.dmaMst.D.ready := 
     Mux1H(Seq(
       ( stateCur === stateRx ) -> true.B,
-      ( stateCur === stateTx ) -> txBuff.io.enq.data.ready,
+      ( stateCur === stateTx ) -> txBuff.io.enq.req.ready,
     ))
 
 
@@ -168,3 +149,11 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
 }
 
 
+
+
+trait SwitchMuxDMATx{ this: SwitchMuxBase =>
+
+}
+
+class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchMuxBase(TLEdgeOut)
+with SwitchMuxDMATx

src/main/scala/Switch/TxBuff.scala

@@ -3,14 +3,14 @@ package Switch
 import chisel3._
 import chisel3.util._
 
+import MAC._
 
 
 
-
+// class Transmit_Req_Bundle extends Bundle{
-class Transmit_Req_Bundle extends Bundle{
+//   // val txLength       = UInt(16.W)
-  val txLength       = UInt(16.W)
+//   val PerPacketCrcEn = Bool()
-  val PerPacketCrcEn = Bool()
+// }
-}
 
 class Transmit_Resp_Bundle extends Bundle{
   val RetryLimit       = Bool()
@@ -22,8 +22,7 @@ class Transmit_Resp_Bundle extends Bundle{
 }
 
 class Transmit_Bundle extends Bundle{
-  val data = Decoupled(UInt(8.W))
+  val req = Decoupled(new Mac_Stream_Bundle)
-  val req  = Decoupled(new Transmit_Req_Bundle)
   val resp = Flipped(Decoupled(new Transmit_Resp_Bundle))
 }
 
@@ -36,63 +35,36 @@ class TxBuffIO extends Bundle{
 abstract class TxBuffBase extends Module{
   val io: TxBuffIO = IO(new TxBuffIO)
 
-
+  val buff = Module(new Queue( new Mac_Stream_Bundle, 2048 ))
-
-  val buff = Module(new Queue( UInt(8.W), 2048 ))
-  val reqInfo = Reg(new Transmit_Req_Bundle)
-  val respInfo = Reg(new Transmit_Resp_Bundle)
   val enqCnt = Reg(UInt(16.W))
-  val deqReqValid = RegInit(false.B)
-
-
-
 
 }
 
 
 trait TxBuffEnq{ this: TxBuffBase =>
-    io.enq.data <> buff.io.enq
+    io.enq.req <> buff.io.enq
 
 
     when( io.enq.req.fire ){
-      enqCnt := 0.U
+      when( io.enq.req.bits.isStart ) {
-      reqInfo := io.enq.req.bits
+        enqCnt := 0.U
-    } .elsewhen( io.enq.data.fire ){
+      } .elsewhen( io.enq.req.bits.isLast ){
-      enqCnt := enqCnt + 1.U
+
+      } .otherwise{
+        enqCnt := enqCnt + 1.U        
+      }
     } 
 
-
-  io.enq.req.ready := ~buff.io.deq.valid
-
-
-  when( io.deq.req.fire ){
-    deqReqValid := false.B
-  } .elsewhen( io.enq.data.fire && enqCnt === 32.U ) {
-    deqReqValid := true.B
-  }
-
 }
 
 trait TxBuffDeq{ this: TxBuffBase =>
-  val isBusy = RegInit(false.B)
-
-  when( io.deq.req.fire ){
-    assert( ~isBusy )
-    isBusy := true.B
-  } .elsewhen(io.deq.resp.fire){
-    assert( isBusy )
-    isBusy := false.B
-  }
 
   io.deq.resp <> io.enq.resp
 
-  io.deq.req.valid := deqReqValid
-  io.deq.req.bits  := reqInfo
-
-  io.deq.data.bits := buff.io.deq.bits
-  io.deq.data.valid := buff.io.deq.valid & isBusy
-  buff.io.deq.ready := io.deq.data.ready & isBusy
 
+  io.deq.req.bits := buff.io.deq.bits
+  io.deq.req.valid := buff.io.deq.valid
+  buff.io.deq.ready := io.deq.req.ready
 }
 
 

src/main/scala/Switch/mac/MAC.scala

@@ -516,7 +516,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
 
 
-  val txReq_ToAsync = Wire(new AsyncBundle(new TxFifo_Stream_Bundle))
+  val txReq_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
   txReq_ToAsync <> ToAsyncBundle( wishbone.io.txReq )
   withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset) {  
     macTileLinkTx.io.txReq <> FromAsyncBundle( txReq_ToAsync )  
@@ -567,7 +567,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
  
 
-  val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
+  val req_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
   val resp_ToAsync = Wire(new AsyncBundle(Bool()))
   val fateRxRespPort = Wire( Flipped(Decoupled(Bool())) )
   fateRxRespPort.ready := true.B
@@ -586,7 +586,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
 
 
 
-  wishbone.io.LatchedRxLength_rxclk   := macTileLinkRx.io.LatchedRxLength
+  // wishbone.io.LatchedRxLength_rxclk   := macTileLinkRx.io.LatchedRxLength
   wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
       
 
@@ -608,7 +608,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   macTileLinkRx.io.RxEndFrm := RxEndFrm
 
 
-  macTileLinkRx.io.RxLength     := RxByteCnt
+  // macTileLinkRx.io.RxLength     := RxByteCnt
   macTileLinkRx.io.LoadRxStatus := LoadRxStatus
   macTileLinkRx.io.RxStatusIn   := Cat(false.B, false.B, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)
 

src/main/scala/Switch/mac/MacTileLinkRx.scala

@@ -4,8 +4,9 @@ import chisel3._
 import chisel3.util._
 
 
-class RxFifo_Stream_Bundle extends Bundle{
+class Mac_Stream_Bundle extends Bundle{
   val data = UInt(8.W)
+  val isStart = Bool()
   val isLast = Bool()
 }
 
@@ -13,12 +14,12 @@ class RxFifo_Stream_Bundle extends Bundle{
 
 class MacTileLinkRxIO extends Bundle{
 
-  val rxReq = Decoupled(new RxFifo_Stream_Bundle)
+  val rxReq = Decoupled(new Mac_Stream_Bundle)
 
-  val LatchedRxLength = Output(UInt(16.W))
+  // val LatchedRxLength = Output(UInt(16.W))
   val RxStatusInLatched = Output( UInt(9.W) )
 
-  val RxLength = Input(UInt(16.W))
+  // val RxLength = Input(UInt(16.W))
   val LoadRxStatus = Input(Bool())
       val RxStatusIn = Input(UInt(9.W))
 
@@ -40,7 +41,7 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
 
   val ShiftWillEnd = RegInit(false.B)
 
-  val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength   := LatchedRxLength
+  // val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength   := LatchedRxLength
   val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
 
   // val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
@@ -70,9 +71,10 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
     }
 
 
-  val rxFifo = Module(new Queue(new RxFifo_Stream_Bundle, 4))
+  val rxFifo = Module(new Queue(new Mac_Stream_Bundle, 4))
   rxFifo.io.enq.valid := SetWriteRxDataToFifo
   rxFifo.io.enq.bits.data   := io.RxData
+  rxFifo.io.enq.bits.isStart := io.RxStartFrm
   rxFifo.io.enq.bits.isLast := io.RxEndFrm
   assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )
 

src/main/scala/Switch/mac/MacTileLinkTx.scala

@@ -4,16 +4,12 @@ import chisel3._
 import chisel3.util._
 
 
-class TxFifo_Stream_Bundle extends Bundle{
+
-  val data = UInt(8.W)
-  val isStart = Bool()
-  val isLast  = Bool()
-}
 
 
 class MacTileLinkTxIO extends Bundle{
 
-  val txReq  = Flipped(Decoupled(new TxFifo_Stream_Bundle))
+  val txReq  = Flipped(Decoupled(new Mac_Stream_Bundle))
   // val txResp = Decoupled()
 
 
@@ -63,12 +59,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
     TxStartFrm := false.B
   }
 
-          // // Indication of the last word
+
-          // when( (TxEndFrm | io.TxAbort) & Flop ){
-          //   LastWord := false.B
-          // } .elsewhen( io.txReq.fire ){
-          //   LastWord := io.txReq.bits.isLast
-          // }
 
   // Tx end frame generation
   when(Flop & TxEndFrm | io.TxAbort){

src/main/scala/Switch/mac/MacTilelink.scala

@@ -21,16 +21,16 @@ abstract class MacTileLinkBase() extends Module{
 
     val r_RxEn    = Input(Bool())         // Receive enable
 
-    val rxReq = Flipped(Decoupled(new RxFifo_Stream_Bundle))
+    val rxReq = Flipped(Decoupled(new Mac_Stream_Bundle))
     val rxResp = Decoupled(new Bool())
 
-    val LatchedRxLength_rxclk = Input(UInt(16.W))
+    // val LatchedRxLength_rxclk = Input(UInt(16.W))
     val RxStatusInLatched_rxclk = Input(UInt(9.W))
     val RxReady = Output(Bool())
 
 
 
-    val txReq = Decoupled(new TxFifo_Stream_Bundle)
+    val txReq = Decoupled(new Mac_Stream_Bundle)
 
     // val TxEndFrm_wb = Output(Bool())
 
@@ -70,7 +70,7 @@ abstract class MacTileLinkBase() extends Module{
 
   val rxBuffCtrlValid = RegInit(false.B)
   io.rxEnq.ctrl.valid := rxBuffCtrlValid
-  io.rxEnq.ctrl.bits.LatchedRxLength   := RegEnable(io.LatchedRxLength_rxclk,   ShiftEndedSyncPluse )
+  // io.rxEnq.ctrl.bits.LatchedRxLength   := RegEnable(io.LatchedRxLength_rxclk,   ShiftEndedSyncPluse )
   io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse )
 
 
@@ -85,14 +85,14 @@ abstract class MacTileLinkBase() extends Module{
   // RxReady generation
   when(ShiftEndedSyncPluse ){
     RxReady := false.B
-  } .elsewhen( io.r_RxEn & (io.rxEnq.data.ready) ){
+  } .elsewhen( io.r_RxEn & (io.rxEnq.req.ready) ){
     RxReady := true.B
   }
 
 
-  io.rxEnq.data.bits  := io.rxReq.bits.data
+  io.rxEnq.req.bits  := io.rxReq.bits
-  io.rxEnq.data.valid := io.rxReq.valid
+  io.rxEnq.req.valid := io.rxReq.valid
-  io.rxReq.ready      := io.rxEnq.data.ready
+  io.rxReq.ready      := io.rxEnq.req.ready
 
   val rxRespValid = RegInit(false.B)
   when( io.rxResp.fire ){
@@ -103,7 +103,7 @@ abstract class MacTileLinkBase() extends Module{
   io.rxResp.valid := rxRespValid
   io.rxResp.bits  := DontCare
 
-  assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" )
+  assert( ~(io.rxEnq.req.valid & ~io.rxEnq.req.ready), "Assert Failed, rx overrun!" )
 
 
 
@@ -125,42 +125,40 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-  val TxStartFrm_wb = RegInit(false.B)
+  // val TxStartFrm_wb = RegInit(false.B)
-  val TxEndFrm_wb = RegInit(false.B)//; io.TxEndFrm_wb := TxEndFrm_wb
+  // val TxEndFrm_wb = RegInit(false.B)
 
-  val TxLength = RegInit(0.U(16.W))
+  // val TxLength = RegInit(0.U(16.W))
-  val LatchedTxLength = RegInit(0.U(16.W))
 
   val txDonePulse                 = io.TxDoneSync              & ~RegNext(io.TxDoneSync,  false.B)
   val txAbortPulse                = io.TxAbortSync             & ~RegNext(io.TxAbortSync, false.B)
 
   
-  io.PerPacketCrcEn  := RegEnable(io.txDeq.req.bits.PerPacketCrcEn, false.B, io.txDeq.req.fire)
+  io.PerPacketCrcEn  := false.B
 
-  when( io.txDeq.req.fire ){
+  // when( io.txDeq.req.fire ){
-    TxStartFrm_wb := true.B
+  //   TxStartFrm_wb := true.B
-  } .elsewhen(io.txReq.fire){
+  // } .elsewhen(io.txReq.fire){
-    TxStartFrm_wb := false.B
+  //   TxStartFrm_wb := false.B
-  }
+  // }
 
 
-    when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
+    // when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
-      TxEndFrm_wb := true.B
+    //   TxEndFrm_wb := true.B
-    } .elsewhen(txDonePulse | txAbortPulse){
+    // } .elsewhen(txDonePulse | txAbortPulse){
-      TxEndFrm_wb := false.B
+    //   TxEndFrm_wb := false.B
-    }
+    // }
 
-  when( io.txDeq.req.fire ){
+  //     val TxLength = RegInit(0.U(16.W))
-
+  // when( io.txDeq.req.fire ){
-    TxLength        := io.txDeq.req.bits.txLength
+  //   TxLength        := io.txDeq.req.bits.txLength
-    LatchedTxLength := io.txDeq.req.bits.txLength
+  // } .elsewhen( io.txDeq.data.fire ){
-  } .elsewhen( io.txDeq.data.fire ){
+  //   when( TxLength < 1.U ){
-    when( TxLength < 1.U ){
+  //     TxLength := 0.U
-      TxLength := 0.U
+  //   } .otherwise{
-    } .otherwise{
+  //     TxLength := TxLength - 1.U    // Length is subtracted at the data request
-      TxLength := TxLength - 1.U    // Length is subtracted at the data request
+  //   }
-    }
+  // }
-  }
 
 
   val txRespValid = RegInit(false.B)
@@ -195,13 +193,13 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-  io.txReq.bits.isLast  := TxEndFrm_wb
+  // io.txReq.bits.isLast  := TxEndFrm_wb
-  io.txReq.bits.data    := io.txDeq.data.bits
-  io.txReq.bits.isStart := TxStartFrm_wb
-  io.txReq.valid        := io.txDeq.data.valid
-  io.txDeq.data.ready   := io.txReq.ready
 
+  // io.txReq.bits.isStart := TxStartFrm_wb
+  // io.txReq.valid        := io.txDeq.data.valid
+  // io.txDeq.data.ready   := io.txReq.ready
 
+  io.txReq <> io.txDeq.req