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解耦rx/txlength，txcrc，后面应该整合tilelink模块，统一dma与mac

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This commit is contained in:
RuigeLee
2023-10-27 18:27:58 +08:00
parent ada2f25ff3
commit beedc98977
9 changed files with 313 additions and 193 deletions
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8
src/main/scala/Switch/mac/MAC.scala
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@@ -516,7 +516,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
val txReq_ToAsync = Wire(new AsyncBundle(new TxFifo_Stream_Bundle))
val txReq_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
txReq_ToAsync <> ToAsyncBundle( wishbone.io.txReq )
withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset) {
macTileLinkTx.io.txReq <> FromAsyncBundle( txReq_ToAsync )
@@ -567,7 +567,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
val req_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
val resp_ToAsync = Wire(new AsyncBundle(Bool()))
val fateRxRespPort = Wire( Flipped(Decoupled(Bool())) )
fateRxRespPort.ready := true.B
@@ -586,7 +586,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
// wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
@@ -608,7 +608,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macTileLinkRx.io.RxEndFrm := RxEndFrm
macTileLinkRx.io.RxLength := RxByteCnt
// macTileLinkRx.io.RxLength := RxByteCnt
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
macTileLinkRx.io.RxStatusIn := Cat(false.B, false.B, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)

14
src/main/scala/Switch/mac/MacTileLinkRx.scala
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@@ -4,8 +4,9 @@ import chisel3._
import chisel3.util._
class RxFifo_Stream_Bundle extends Bundle{
class Mac_Stream_Bundle extends Bundle{
val data = UInt(8.W)
val isStart = Bool()
val isLast = Bool()
}
@@ -13,12 +14,12 @@ class RxFifo_Stream_Bundle extends Bundle{
class MacTileLinkRxIO extends Bundle{
val rxReq = Decoupled(new RxFifo_Stream_Bundle)
val rxReq = Decoupled(new Mac_Stream_Bundle)
val LatchedRxLength = Output(UInt(16.W))
// val LatchedRxLength = Output(UInt(16.W))
val RxStatusInLatched = Output( UInt(9.W) )
val RxLength = Input(UInt(16.W))
// val RxLength = Input(UInt(16.W))
val LoadRxStatus = Input(Bool())
val RxStatusIn = Input(UInt(9.W))
@@ -40,7 +41,7 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
val ShiftWillEnd = RegInit(false.B)
val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
// val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
// val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
@@ -70,9 +71,10 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
}
val rxFifo = Module(new Queue(new RxFifo_Stream_Bundle, 4))
val rxFifo = Module(new Queue(new Mac_Stream_Bundle, 4))
rxFifo.io.enq.valid := SetWriteRxDataToFifo
rxFifo.io.enq.bits.data := io.RxData
rxFifo.io.enq.bits.isStart := io.RxStartFrm
rxFifo.io.enq.bits.isLast := io.RxEndFrm
assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )

15
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -4,16 +4,12 @@ import chisel3._
import chisel3.util._
class TxFifo_Stream_Bundle extends Bundle{
val data = UInt(8.W)
val isStart = Bool()
val isLast = Bool()
}
class MacTileLinkTxIO extends Bundle{
val txReq = Flipped(Decoupled(new TxFifo_Stream_Bundle))
val txReq = Flipped(Decoupled(new Mac_Stream_Bundle))
// val txResp = Decoupled()
@@ -63,12 +59,7 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
TxStartFrm := false.B
}
// // Indication of the last word
// when( (TxEndFrm | io.TxAbort) & Flop ){
// LastWord := false.B
// } .elsewhen( io.txReq.fire ){
// LastWord := io.txReq.bits.isLast
// }
// Tx end frame generation
when(Flop & TxEndFrm | io.TxAbort){

78
src/main/scala/Switch/mac/MacTilelink.scala
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@@ -21,16 +21,16 @@ abstract class MacTileLinkBase() extends Module{
val r_RxEn = Input(Bool()) // Receive enable
val rxReq = Flipped(Decoupled(new RxFifo_Stream_Bundle))
val rxReq = Flipped(Decoupled(new Mac_Stream_Bundle))
val rxResp = Decoupled(new Bool())
val LatchedRxLength_rxclk = Input(UInt(16.W))
// val LatchedRxLength_rxclk = Input(UInt(16.W))
val RxStatusInLatched_rxclk = Input(UInt(9.W))
val RxReady = Output(Bool())
val txReq = Decoupled(new TxFifo_Stream_Bundle)
val txReq = Decoupled(new Mac_Stream_Bundle)
// val TxEndFrm_wb = Output(Bool())
@@ -70,7 +70,7 @@ abstract class MacTileLinkBase() extends Module{
val rxBuffCtrlValid = RegInit(false.B)
io.rxEnq.ctrl.valid := rxBuffCtrlValid
io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse )
// io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse )
io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse )
@@ -85,14 +85,14 @@ abstract class MacTileLinkBase() extends Module{
// RxReady generation
when(ShiftEndedSyncPluse ){
RxReady := false.B
} .elsewhen( io.r_RxEn & (io.rxEnq.data.ready) ){
} .elsewhen( io.r_RxEn & (io.rxEnq.req.ready) ){
RxReady := true.B
}
io.rxEnq.data.bits := io.rxReq.bits.data
io.rxEnq.data.valid := io.rxReq.valid
io.rxReq.ready := io.rxEnq.data.ready
io.rxEnq.req.bits := io.rxReq.bits
io.rxEnq.req.valid := io.rxReq.valid
io.rxReq.ready := io.rxEnq.req.ready
val rxRespValid = RegInit(false.B)
when( io.rxResp.fire ){
@@ -103,7 +103,7 @@ abstract class MacTileLinkBase() extends Module{
io.rxResp.valid := rxRespValid
io.rxResp.bits := DontCare
assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" )
assert( ~(io.rxEnq.req.valid & ~io.rxEnq.req.ready), "Assert Failed, rx overrun!" )
@@ -125,42 +125,40 @@ abstract class MacTileLinkBase() extends Module{
val TxStartFrm_wb = RegInit(false.B)
val TxEndFrm_wb = RegInit(false.B)//; io.TxEndFrm_wb := TxEndFrm_wb
// val TxStartFrm_wb = RegInit(false.B)
// val TxEndFrm_wb = RegInit(false.B)
val TxLength = RegInit(0.U(16.W))
val LatchedTxLength = RegInit(0.U(16.W))
// val TxLength = RegInit(0.U(16.W))
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
io.PerPacketCrcEn := RegEnable(io.txDeq.req.bits.PerPacketCrcEn, false.B, io.txDeq.req.fire)
io.PerPacketCrcEn := false.B
when( io.txDeq.req.fire ){
TxStartFrm_wb := true.B
} .elsewhen(io.txReq.fire){
TxStartFrm_wb := false.B
}
// when( io.txDeq.req.fire ){
// TxStartFrm_wb := true.B
// } .elsewhen(io.txReq.fire){
// TxStartFrm_wb := false.B
// }
when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
TxEndFrm_wb := true.B
} .elsewhen(txDonePulse | txAbortPulse){
TxEndFrm_wb := false.B
}
// when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
// TxEndFrm_wb := true.B
// } .elsewhen(txDonePulse | txAbortPulse){
// TxEndFrm_wb := false.B
// }
when( io.txDeq.req.fire ){
TxLength := io.txDeq.req.bits.txLength
LatchedTxLength := io.txDeq.req.bits.txLength
} .elsewhen( io.txDeq.data.fire ){
when( TxLength < 1.U ){
TxLength := 0.U
} .otherwise{
TxLength := TxLength - 1.U // Length is subtracted at the data request
}
}
// val TxLength = RegInit(0.U(16.W))
// when( io.txDeq.req.fire ){
// TxLength := io.txDeq.req.bits.txLength
// } .elsewhen( io.txDeq.data.fire ){
// when( TxLength < 1.U ){
// TxLength := 0.U
// } .otherwise{
// TxLength := TxLength - 1.U // Length is subtracted at the data request
// }
// }
val txRespValid = RegInit(false.B)
@@ -195,13 +193,13 @@ abstract class MacTileLinkBase() extends Module{
io.txReq.bits.isLast := TxEndFrm_wb
io.txReq.bits.data := io.txDeq.data.bits
io.txReq.bits.isStart := TxStartFrm_wb
io.txReq.valid := io.txDeq.data.valid
io.txDeq.data.ready := io.txReq.ready
// io.txReq.bits.isLast := TxEndFrm_wb
// io.txReq.bits.isStart := TxStartFrm_wb
// io.txReq.valid := io.txDeq.data.valid
// io.txDeq.data.ready := io.txReq.ready
io.txReq <> io.txDeq.req