合并bacon_dev分支的修改:1.协议基本运转;2.增加make debug_hlm
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@@ -1,49 +1,2 @@
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#include <stdint.h>
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#include "tl2cdr.h"
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#ifndef TL2CDR_BASE
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#error TL2CDR Base address not define!!!
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#endif
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#ifdef OLD_CODE
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volatile uint32_t * const cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
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volatile uint32_t * const cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
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volatile uint32_t * const cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
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volatile uint32_t * const cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
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volatile uint32_t * const cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
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volatile uint32_t * const cdr_rxLen = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
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volatile uint32_t * const cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
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volatile uint32_t * const cdr_IsLast = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
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volatile uint32_t * const cdr_rxCrc = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
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volatile uint32_t * const cdr_txCrc = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
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#endif
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volatile uint32_t * const tx0_softReset = (uint32_t*)( TL2CDR_BASE + TX0_WriteSoftReset );
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volatile uint32_t * const tx0_txLen = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxLen );
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volatile uint32_t * const tx0_txFifo = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxFifo );
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volatile uint32_t * const tx0_txCrc = (uint32_t*)( TL2CDR_BASE + TX0_ReadTxCrc );
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volatile uint32_t * const tx1_softReset = (uint32_t*)( TL2CDR_BASE + TX1_WriteSoftReset );
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volatile uint32_t * const tx1_txLen = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxLen );
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volatile uint32_t * const tx1_txFifo = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxFifo );
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volatile uint32_t * const tx1_txCrc = (uint32_t*)( TL2CDR_BASE + TX1_ReadTxCrc );
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volatile uint32_t * const rx0_softReset = (uint32_t*)( TL2CDR_BASE + RX0_WriteSoftReset );
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volatile uint32_t * const rx0_rxLen = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxLen );
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volatile uint32_t * const rx0_rxFifo = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxFifo );
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volatile uint32_t * const rx0_rxCrc = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxCrc );
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volatile uint32_t * const rx0_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX0_WrtieLimitTimerAim );
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volatile uint32_t * const rx0_rxTxPair = (uint32_t*)( TL2CDR_BASE + RX0_WriteLimitTxPair );
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volatile uint32_t * const rx1_softReset = (uint32_t*)( TL2CDR_BASE + RX1_WriteSoftReset );
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volatile uint32_t * const rx1_rxLen = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxLen );
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volatile uint32_t * const rx1_rxFifo = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxFifo );
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volatile uint32_t * const rx1_rxCrc = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxCrc );
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volatile uint32_t * const rx1_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX1_WrtieLimitTimerAim );
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volatile uint32_t * const rx1_rxTxPair = (uint32_t*)( TL2CDR_BASE + RX1_WriteLimitTxPair );
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volatile uint32_t * const HLM_status = (uint32_t*)( TL2CDR_BASE + HLM_ReadStatus );
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volatile uint32_t * const HLM_isLast = (uint32_t*)( TL2CDR_BASE + HLM_ReadIsLast );
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@@ -5,36 +5,6 @@
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#include <stdint.h>
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#endif
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#define TL2CDR_BASE 0x10000000U
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#define TX0_WriteSoftReset 0x00U
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#define TX0_WriteTxLen 0x04U
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#define TX0_WriteTxFifo 0x08U
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#define TX0_ReadTxCrc 0x0CU
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#define TX1_WriteSoftReset 0x10U
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#define TX1_WriteTxLen 0x14U
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#define TX1_WriteTxFifo 0x18U
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#define TX1_ReadTxCrc 0x1CU
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#define RX0_WriteSoftReset 0x20U
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#define RX0_ReadRxLen 0x24U
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#define RX0_ReadRxFifo 0x28U
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#define RX0_ReadRxCrc 0x2CU
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#define RX0_WrtieLimitTimerAim 0x30U
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#define RX0_WriteLimitTxPair 0x34U
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#define RX1_WriteSoftReset 0x40U
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#define RX1_ReadRxLen 0x44U
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#define RX1_ReadRxFifo 0x48U
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#define RX1_ReadRxCrc 0x4CU
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#define RX1_WrtieLimitTimerAim 0x50U
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#define RX1_WriteLimitTxPair 0x54U
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#define HLM_ReadStatus 0x58U
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#define HLM_ReadIsLast 0x5CU
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#define HLM_TX_FIFO_LEN 16U
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#define HLM_RX_FIFO_LEN 16U
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@@ -52,33 +22,145 @@
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#define HLM_TX0_FIFO_LEFT(s) (((s) >> (8 + 10)) & 0x1f)
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#define HLM_TX1_FIFO_LEFT(s) (((s) >> (8 + 15)) & 0x1f)
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#define HLM_INT_TX1_END (1U<<11U)
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#define HLM_INT_TX0_END (1U<<10U)
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#define HLM_INT_RX1_ERR (1U<<9U)
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#define HLM_INT_RX0_ERR (1U<<8U)
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#define HLM_INT_RX1_START (1U<<7U)
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#define HLM_INT_RX0_START (1U<<6U)
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#define HLM_INT_RX1_END (1U<<5U)
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#define HLM_INT_RX0_END (1U<<4U)
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#define HLM_INT_TX1_FIFO_DEQ (1U<<3U)
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#define HLM_INT_TX0_FIFO_DEQ (1U<<2U)
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#define HLM_INT_RX1_FIFO_ENQ (1U<<1U)
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#define HLM_INT_RX0_FIFO_ENQ (1U<<0U)
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#ifndef __ASSEMBLER__
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extern volatile uint32_t * const tx0_softReset;
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extern volatile uint32_t * const tx0_txLen;
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extern volatile uint32_t * const tx0_txFifo;
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extern volatile uint32_t * const tx0_txCrc;
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#define i_tx0_softReset(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x00, x0, %0, x0" :: "r"(rs1))
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#define i_tx0_txLen(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x01, x0, %0, x0" :: "r"(rs1))
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#define i_tx0_txFifo(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x02, x0, %0, x0" :: "r"(rs1))
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#define i_tx0_txCrc(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x03, %0, x0, x0" :"=r"(rd))
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#define i_tx0_clear_timer(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x04, x0, %0, x0" :: "r"(rs1))
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#define i_tx0_read_timer(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x04, %0, x0, x0" :"=r"(rd))
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extern volatile uint32_t * const tx1_softReset;
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extern volatile uint32_t * const tx1_txLen;
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extern volatile uint32_t * const tx1_txFifo;
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extern volatile uint32_t * const tx1_txCrc;
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#define i_tx1_softReset(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x05, x0, %0, x0" :: "r"(rs1))
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#define i_tx1_txLen(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x06, x0, %0, x0" :: "r"(rs1))
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#define i_tx1_txFifo(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x07, x0, %0, x0" :: "r"(rs1))
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#define i_tx1_txCrc(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x08, %0, x0, x0" :"=r"(rd))
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#define i_tx1_clear_timer(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x09, x0, %0, x0" :: "r"(rs1))
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#define i_tx1_read_timer(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x09, %0, x0, x0" :"=r"(rd))
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extern volatile uint32_t * const rx0_softReset;
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extern volatile uint32_t * const rx0_rxLen;
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extern volatile uint32_t * const rx0_rxFifo;
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extern volatile uint32_t * const rx0_rxCrc;
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extern volatile uint32_t * const rx0_rxTimerAim;
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extern volatile uint32_t * const rx0_rxTxPair;
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#define i_rx0_softReset(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x0A, x0, %0, x0" :: "r"(rs1))
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#define i_rx0_rxLen(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x0B, %0, x0, x0" :"=r"(rd))
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#define i_rx0_rxFifo(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x0C, %0, x0, x0" :"=r"(rd))
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#define i_rx0_rxCrc(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x0D, %0, x0, x0" :"=r"(rd))
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#define i_rx0_limitTime(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x0E, x0, %0, x0" :: "r"(rs1))
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#define i_rx0_txPair(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x0F, x0, %0, x0" :: "r"(rs1))
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#define i_rx1_softReset(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x10, x0, %0, x0" :: "r"(rs1))
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#define i_rx1_rxLen(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x11, %0, x0, x0" :"=r"(rd))
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#define i_rx1_rxFifo(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x12, %0, x0, x0" :"=r"(rd))
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#define i_rx1_rxCrc(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x13, %0, x0, x0" :"=r"(rd))
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#define i_rx1_limitTime(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x14, x0, %0, x0" :: "r"(rs1))
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#define i_rx1_txPair(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x15, x0, %0, x0" :: "r"(rs1))
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#define i_hlm_status(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x16, %0, x0, x0" :"=r"(rd))
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#define i_hlm_clear_intflag(rs1) \
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__asm__ volatile (".insn r 0x0B, 2, 0x17, x0, %0, x0" :: "r"(rs1))
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#define i_hlm_read_intflag(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x17, %0, x0, x0" :"=r"(rd))
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#define i_hlm_isLast(rd) \
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__asm__ volatile (".insn r 0x0B, 4, 0x18, %0, x0, x0" :"=r"(rd))
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#else
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#define i_tx0_softReset(rs1) \
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.insn r 0x0B, 2, 0x00, x0, rs1, x0
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#define i_tx0_txLen(rs1) \
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.insn r 0x0B, 2, 0x01, x0, rs1, x0
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#define i_tx0_txFifo(rs1) \
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.insn r 0x0B, 2, 0x01, x0, rs1, x0
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#define i_tx0_txCrc(rd) \
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.insn r 0x0B, 4, 0x03, rd, x0, x0
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#define i_tx0_clear_timer(rs1) \
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.insn r 0x0B, 2, 0x04, x0, rs1, x0
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#define i_tx0_read_timer(rd) \
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.insn r 0x0B, 4, 0x04, rd, x0, x0
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#define i_tx1_softReset(rs1) \
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.insn r 0x0B, 2, 0x05, x0, rs1, x0
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#define i_tx1_txLen(rs1) \
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.insn r 0x0B, 2, 0x06, x0, rs1, x0
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#define i_tx1_txFifo(rs1) \
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.insn r 0x0B, 2, 0x07, x0, rs1, x0
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#define i_tx1_txCrc(rd) \
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.insn r 0x0B, 4, 0x08, rd, x0, x0
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#define i_tx1_clear_timer(rs1) \
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.insn r 0x0B, 2, 0x09, x0, rs1, x0
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#define i_tx1_read_timer(rd) \
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.insn r 0x0B, 4, 0x09, rd, x0, x0
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#define i_rx0_softReset(rs1) \
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.insn r 0x0B, 2, 0x0A, x0, rs1, x0
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#define i_rx0_rxLen(rd) \
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.insn r 0x0B, 4, 0x0B, rd, x0, x0
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#define i_rx0_rxFifo(rd) \
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.insn r 0x0B, 4, 0x0C, rd, x0, x0
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#define i_rx0_rxCrc(rd) \
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.insn r 0x0B, 4, 0x0D, rd, x0, x0
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#define i_rx0_limitTime(rs1) \
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.insn r 0x0B, 2, 0x0E, x0, rs1, x0
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#define i_rx0_txPair(rs1) \
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.insn r 0x0B, 2, 0x0F, x0, rs1, x0
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#define i_rx1_softReset(rs1) \
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.insn r 0x0B, 2, 0x10, x0, rs1, x0
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#define i_rx1_rxLen(rd) \
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.insn r 0x0B, 4, 0x11, rd, x0, x0
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#define i_rx1_rxFifo(rd) \
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.insn r 0x0B, 4, 0x12, rd, x0, x0
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#define i_rx1_rxCrc(rd) \
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.insn r 0x0B, 4, 0x13, rd, x0, x0
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#define i_rx1_limitTime(rs1) \
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.insn r 0x0B, 2, 0x14, x0, rs1, x0
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#define i_rx1_txPair(rs1) \
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.insn r 0x0B, 2, 0x15, x0, rs1, x0
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#define i_hlm_status(rd) \
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.insn r 0x0B, 4, 0x16, rd, x0, x0
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#define i_hlm_clear_intflag(rs1) \
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.insn r 0x0B, 2, 0x17, x0, rs1, x0
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#define i_hlm_read_intflag(rd) \
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.insn r 0x0B, 4, 0x17, rd, x0, x0
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#define i_hlm_isLast(rd) \
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.insn r 0x0B, 4, 0x18, rd, x0, x0
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extern volatile uint32_t * const rx1_softReset;
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extern volatile uint32_t * const rx1_rxLen;
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extern volatile uint32_t * const rx1_rxFifo;
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extern volatile uint32_t * const rx1_rxCrc;
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extern volatile uint32_t * const rx1_rxTimerAim;
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extern volatile uint32_t * const rx1_rxTxPair;
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extern volatile uint32_t * const HLM_status;
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extern volatile uint32_t * const HLM_isLast;
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#endif
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#endif
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