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合并bacon_dev分支的修改:1.协议基本运转;2.增加make debug_hlm

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bacon
2025-02-27 12:55:34 +08:00
parent b167d3affa
commit be7adef4aa
14 changed files with 1060 additions and 291 deletions
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52
tb/sw/src/hlmSvrOpt.S
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@@ -73,7 +73,8 @@ init_func:
la x17, _rv32i_plic_handle
mv a0, x17
li x29, TL2CDR_BASE
//li x29, TL2CDR_BASE
ret
//主站启动发送数据
@@ -88,11 +89,13 @@ send_data_func:
//*tx0_txLen = 8 + tx_len; //前导+长度命令
mv x16, a2
addi x17, x16, 8
sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
i_tx0_txLen(x17)
//*tx0_txFifo = (tx_len << 20) | (0 << 16) | 0x0000;
slli x17, x16, 20
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
i_tx0_txFifo(x17)
li a0, 1
ret
@@ -131,23 +134,30 @@ slave_work_func:
#else
slave_work_func:
1:
lw x18, HLM_ReadStatus(x29)
//lw x18, HLM_ReadStatus(x29)
i_hlm_status(x18)
andi x19, x18, HLM_RX0_VALID
beqz x19, 1b
lw x20, RX0_ReadRxFifo(x29)
//lw x20, RX0_ReadRxFifo(x29)
i_rx0_rxFifo(x20)
srli x19, x20, 20
addi x19, x19, 4
sw x19, TX1_WriteTxLen(x29)
sw x20, TX1_WriteTxFifo(x29)
//sw x19, TX1_WriteTxLen(x29)
i_tx1_txLen(x29)
//sw x20, TX1_WriteTxFifo(x29)
i_tx1_txFifo(x29)
li x21, 4
1:
lw x18, HLM_ReadStatus(x29)
//lw x18, HLM_ReadStatus(x29)
i_hlm_status(x29)
andi x18, x18, HLM_RX0_VALID
beqz x18, 1b
lw x20, RX0_ReadRxFifo(x29)
sw x20, TX1_WriteTxFifo(x29)
//lw x20, RX0_ReadRxFifo(x29)
i_rx0_rxFifo(x29)
//sw x20, TX1_WriteTxFifo(x29)
i_tx1_txFifo(x29)
addi x21, x21, 4
bltu x21, x19, 1b
@@ -212,11 +222,13 @@ send_data_func:
//*tx0_txLen = 8 + tx_len; //前导+长度命令
mv x16, a2
addi x17, x16, 8
sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
i_tx0_txLen(x17)
//*tx0_txFifo = (tx_len << 20) | (0 << 16) | 0x0000;
slli x17, x16, 20
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
i_tx0_txFifo(x17)
//*tx0_txFifo = data[0]
#lw x17, 0(REG_tx_data)
@@ -256,11 +268,13 @@ exit_handle:
isr_tx0_end_hdl:
#li x17, 1
#sw x17, TX0_WriteSoftReset(REG_TL2CDR_BASE)
//i_tx0_softReset(x17)
mret
isr_tx1_end_hdl:
#li x17, 1
#sw x17, TX0_WriteSoftReset(REG_TL2CDR_BASE)
#sw x17, TX1_WriteSoftReset(REG_TL2CDR_BASE)
//i_tx1_softReset(x17)
mret
isr_rx0_err_hdl:
@@ -273,7 +287,8 @@ isr_rx0_start_hdl:
mret
isr_rx1_start_hdl:
lw x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
//lw x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
i_rx1_rxLen(x22)
sw x22, 0(REG_rx_data)
add REG_rx_data, REG_rx_data, REG_4
mret
@@ -287,7 +302,9 @@ isr_rx1_end_hdl:
isr_tx0_deq_hdl:
beqz REG_tx_data_len, 1f //if (REG_tx_data_len > 0)
lw x17, 0(REG_tx_data)
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
i_tx0_txFifo(x17)
add REG_tx_data, REG_tx_data, REG_4
sub REG_tx_data_len, REG_tx_data_len, REG_4
@@ -301,9 +318,10 @@ isr_rx0_enq_hdl:
mret
isr_rx1_enq_hdl:
lw x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
//lw x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
i_rx1_rxFifo(x17)
sw x17, 0(REG_rx_data)
add REG_rx_data, REG_rx_data, REG_4
//add REG_rx_data, REG_rx_data, REG_4
mret
isr_hdl_table: