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合并bacon_dev分支的修改:1.协议基本运转;2.增加make debug_hlm

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This commit is contained in:
bacon
2025-02-27 12:55:34 +08:00
parent b167d3affa
commit be7adef4aa
14 changed files with 1060 additions and 291 deletions
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5
tb/sw/src/MstMain.c
View File

@@ -5,6 +5,8 @@
#include "halfLvdsMacSvr.h"
#include "plic.h"
uint8_t sys_stack[STACK_SIZE] __attribute__((aligned(0x100), section(".sys_stack")));
//-------------------------------------------------------------------
//internal function
static uint32_t init_plic(void);
@@ -33,6 +35,7 @@ void main()
uint32_t init_plic(void)
{
#if 0
/*初始化plic*/
*plic_enable_0_31 = 1 << CDR_INT_TX0END
//| 1 << CDR_INT_TX1END
@@ -68,7 +71,7 @@ uint32_t init_plic(void)
*plic_threshold_0 = 0;
#endif
return 0;
}

12
tb/sw/src/SlvMain.c
View File

@@ -8,6 +8,8 @@
#include "sysDef.h"
#include "plic.h"
uint8_t sys_stack[STACK_SIZE] __attribute__((aligned(0x100), section(".sys_stack")));
static void error();
static uint32_t init_plic(void);
@@ -16,12 +18,6 @@ void main()
{
init_plic();
//复位脉冲
*tx0_softReset = 1;
*tx1_softReset = 1;
*rx0_softReset = 1;
*rx1_softReset = 1;
//tx0 下行
//tx1 上行
@@ -42,7 +38,7 @@ void error() {
uint32_t init_plic(void)
{
#if 0
/*初始化plic*/
*plic_enable_0_31 = 1 << CDR_INT_TX0END
| 1 << CDR_INT_TX1END
@@ -77,7 +73,7 @@ uint32_t init_plic(void)
plic_priority[CDR_INT_RX1_FIFO_ENQ] = 1;
*plic_threshold_0 = 0;
#endif
return 0;
}

593
tb/sw/src/halfLvdsMacSvr.c
View File

@@ -5,6 +5,12 @@
#include "plic.h"
#include "clint.h"
#define DETECT_DEVICE_PKT_LEN 4
#define MAGIC_NUM 0xa53fd1a0U
#define DETECT_DEV_INTERVAL ((40)/CLINT_MTIME_TICK_PERIOD)
//-------------------------------------------------------------------
uint8_t MST_TX_BUF[TX_BUF_NUM * TX_BUF_MAX_LEN] __attribute__((aligned(32)));
uint8_t MST_RX_BUF[RX_BUF_NUM * RX_BUF_MAX_LEN] __attribute__((aligned(32)));
@@ -13,96 +19,202 @@ uint8_t MST_RX_BUF[RX_BUF_NUM * RX_BUF_MAX_LEN] __attribute__((aligned(32)));
//-------------------------------------------------------------------
extern const uint8_t int_svr_code[];
uint32_t (*sys_call)(uint32_t no, ...);
static uint32_t HLM_slave_poll(void);
volatile uint32_t exti_isr_flag[32] = {0};
uint32_t HLM_poll(uint32_t mode)
{
sys_call = (void *)int_svr_code;
//复位脉冲
*tx0_softReset = 1;
*tx1_softReset = 1;
*rx0_softReset = 1;
*rx1_softReset = 1;
//*tx0_softReset = 1;
i_tx0_softReset(1);
//*tx1_softReset = 1;
i_tx1_softReset(1);
//*rx0_softReset = 1;
i_rx0_softReset(1);
//*rx1_softReset = 1;
i_rx1_softReset(1);
if (mode == WORKMODE_MASTER)
{
uint32_t tx_pkt_len = 1024;
uint32_t rx_pkt_len = 0;
uint32_t rx_start = 0;
uint32_t status;
uint32_t is_exit = 0;
uint32_t seq = 0;
uint32_t i;
uint32_t *tx_data_ptr = (uint32_t *)MST_TX_BUF;
uint32_t *rx_data_ptr = (uint32_t *)MST_RX_BUF;
//准备数据
for (i = 0; i < tx_pkt_len; i++)
MST_TX_BUF[i] = i;
//开始发送工作
*tx0_txLen = tx_pkt_len + 4;
*tx0_txFifo = (tx_pkt_len << 20) | 0;
uint32_t tx_index = 0;
uint32_t rx_index = 0;
for (i = 0; i < HLM_TX_FIFO_LEN - 1; i++)
while (1)
{
if ((tx_index * 4) < tx_pkt_len)
uint32_t tx_pkt_len;
uint32_t rx_pkt_len = 0;
uint32_t rx_start = 0;
uint32_t status;
uint32_t is_exit = 0;
uint32_t intflag;
uint32_t is_tx_crc;
uint32_t is_rx_crc;
uint32_t recv_valid;
uint32_t i;
uint32_t *tx_data_ptr = (uint32_t *)MST_TX_BUF;
uint32_t *rx_data_ptr = (uint32_t *)MST_RX_BUF;
if (seq == 0)
{
*tx0_txFifo = tx_data_ptr[tx_index];
tx_index++;
is_tx_crc = 0;
is_rx_crc = 0;
tx_pkt_len = DETECT_DEVICE_PKT_LEN + 4;
tx_data_ptr[0] = (DETECT_DEVICE_PKT_LEN << 20) | 1;
tx_data_ptr[1] = MAGIC_NUM;
}
else if (seq == 1)
{
is_tx_crc = 1;
is_rx_crc = 1;
tx_pkt_len = 256 + 4;
tx_data_ptr[0] = ((tx_pkt_len - 4) << 20) | 2;
for (i = 4; i < (tx_pkt_len - 4 * is_tx_crc); i++)
MST_TX_BUF[i] = i;
}
else
break;
}
while (!is_exit)
{
status = *HLM_status;
for (i = 0; i < HLM_TX_FIFO_LEN - HLM_TX0_FIFO_LEFT(status); i++)
{
if ((tx_index * 4) < tx_pkt_len)
is_tx_crc = 1;
is_rx_crc = 1;
tx_pkt_len = 5 * 4 + 4;
//准备数据
tx_data_ptr[0] = ((tx_pkt_len - 4) << 20) | 2;
tx_data_ptr[1] = 0; //64bit time hi
tx_data_ptr[2] = 0; //64bit time lo
tx_data_ptr[3] = 0; //delta time
tx_data_ptr[4] = 0; //ctr | dev_num
//tx_data_ptr[5] = 0; //crc
}
//开始发送工作
i_tx0_txLen(tx_pkt_len);
uint32_t tx_index = 0;
uint32_t rx_index = 0;
uint32_t tx_len;
tx_len = is_tx_crc? (tx_pkt_len - 4):tx_pkt_len;
//i_tx0_clear_timer(0);
for (i = 0; i < HLM_TX_FIFO_LEN; i++)
{
if ((tx_index * 4) < tx_len)
{
*tx0_txFifo = tx_data_ptr[tx_index];
i_tx0_txFifo(tx_data_ptr[tx_index]);
tx_index++;
}
else
break;
}
for (i = 0; i < HLM_RX1_FIFO_LEFT(status); i++)
{
//if ((rx_start) && (status & HLM_RX1_VALID))
if (rx_start)
{
rx_data_ptr[rx_index] = *rx1_rxFifo;
if (rx_index == 0)
rx_pkt_len = (rx_data_ptr[rx_index] >> 20) + 4;
rx_index++;
if (rx_pkt_len <= (rx_index * 4))
if (is_tx_crc)
{
rx_start = 0;
rx_index = 0;
is_exit = 1;
break;
uint32_t crc;
i_tx0_txCrc(crc);
i_tx0_txFifo(crc);
tx_index++;
}
break;
}
}
if (exti_isr_flag[CDR_INT_RX1START])
while (!is_exit)
{
exti_isr_flag[CDR_INT_RX1START] = 0;
rx_start = 1;
rx_index = 0;
uint32_t tx_times;
//i_tx1_softReset(1);
i_hlm_status(status);
i_hlm_read_intflag(intflag);
i_hlm_clear_intflag(intflag);
tx_times = HLM_TX_FIFO_LEN - HLM_TX0_FIFO_LEFT(status);
for (i = 0; i < tx_times; i++)
{
if ((tx_index * 4) < tx_len)
{
i_tx0_txFifo(tx_data_ptr[tx_index]);
tx_index++;
}
else
{
if (is_tx_crc && ((tx_index * 4) == tx_len))
{
uint32_t crc;
i_tx0_txCrc(crc);
i_tx0_txFifo(crc);
tx_index++;
}
break;
}
}
for (i = 0; i < HLM_RX1_FIFO_LEFT(status); i++)
{
if (rx_start)
{
if ((rx_pkt_len - 4) == (rx_index * 4))
{
uint32_t crc;
i_rx1_rxCrc(crc);
i_rx1_rxFifo(rx_data_ptr[rx_index]);
if (is_rx_crc)
while (crc != rx_data_ptr[rx_index]);
}
else
{
i_rx1_rxFifo(rx_data_ptr[rx_index]);
}
if (rx_index == 0)
{
rx_pkt_len = (rx_data_ptr[rx_index] >> 20) + 4;
}
rx_index++;
if (rx_pkt_len < (rx_index * 4))
{
rx_start = 0;
rx_index = 0;
break;
}
}
}
//if ((rx_start == 0) && (status & HLM_RX1_VALID))
if (intflag & HLM_INT_RX1_START)
{
//exti_isr_flag[CDR_INT_RX1START] = 0;
rx_start = 1;
rx_index = 0;
}
if (intflag & HLM_INT_RX1_END)
{
is_exit = 1;
i_rx1_softReset(1);
i_tx0_softReset(1);
}
}
if (seq == 0)
{
if ((rx_pkt_len == 8) && ((rx_data_ptr[0] & 0xff) == 0x1) && (rx_data_ptr[1] == MAGIC_NUM))
{
seq = 1;
}
}
else if (seq == 1)
{
}
}
@@ -118,23 +230,19 @@ uint32_t HLM_poll(uint32_t mode)
return 0;
}
#define DETECT_DEVICE_PKT_LEN 4
#define DETECT_DEVICE_PKT_TX_LEN (DETECT_DEVICE_PKT_LEN + 4)
#define MAGIC_NUM 0xa53fd1a0U
#define DETECT_DEV_INTERVAL ((200)/CLINT_MTIME_TICK_PERIOD)
uint32_t HLM_slave_2streams_poll(uint32_t protocol, uint32_t data, uint32_t is_crc);
uint32_t HLM_slave_1stream_poll(uint32_t protocol, uint32_t data, uint32_t is_crc);
uint32_t HLM_slave_poll(void)
{
uint32_t rx_index = 0;
uint32_t tx_pkt_len;
uint32_t rx_pkt_len = 0;
uint32_t down_rx_work = 0;
uint32_t detect_work = 0;
uint32_t downstream_work = 0;
uint32_t hlm_status;
uint32_t is_terminal = 1;
uint32_t detect_result = 0;
uint32_t intflag;
uint32_t protocol = 0;
uint64_t stamp_time;
uint64_t cur_time;
@@ -144,17 +252,19 @@ uint32_t HLM_slave_poll(void)
int i;
*rx0_rxTxPair = 1;
*rx0_rxTimerAim = 0;// 280;
*rx1_rxTxPair = 0;
*rx1_rxTimerAim = 0;
//*rx0_rxTxPair = 1;
i_rx0_txPair(1);
i_rx0_limitTime(0);
i_rx1_txPair(0);
i_rx1_limitTime(0);
//*rx0_rxTimerAim = 0; //240;
//*rx1_rxTxPair = 0;
//*rx1_rxTimerAim = 0;
*plic_enable_0_31 = 0;
stamp_time = read_mtimer();
//set_mtimer(150);
//enable_mtimer_int();
stamp_time = 0; //read_mtimer();
#ifdef __riscv_e
sys_call(SYS_SLAVE_WORK);
@@ -164,88 +274,106 @@ uint32_t HLM_slave_poll(void)
{
if (is_terminal)
{//是终节点
hlm_status = *HLM_status;
if ((!down_rx_work) && (hlm_status & HLM_RX0_VALID))
{
down_rx_work = 1;
}
//status = *HLM_status;
i_hlm_status(hlm_status);
i_hlm_read_intflag(intflag);
for (i = 0; i < HLM_RX0_FIFO_LEFT(hlm_status); i++)
//i_hlm_clear_intflag(intflag);
//if ((!downstream_work) && (hlm_status & HLM_RX0_VALID))
// downstream_work = 1;
if (intflag & HLM_INT_RX0_START)
{
downstream_work = 1;
i_hlm_clear_intflag(HLM_INT_RX0_START);
}
if (downstream_work && (hlm_status & HLM_RX0_VALID))
{
uint32_t data;
if (down_rx_work)
{//处理上行接收
data = *rx0_rxFifo;
if (rx_index == 0)
{
rx_pkt_len = (data >> 20) + 4;
*tx1_txLen = rx_pkt_len;
//rx_pkt_len += 4; //最后是一个0,接收入队列，但不写入tx_fifo
}
rx_index++;
if (rx_pkt_len >= (rx_index * 4))
{
*tx1_txFifo = data;
}
else
{
down_rx_work = 0;
rx_index = 0;
//*rx0_softReset = 1;
break;
}
i_rx0_rxFifo(data);
protocol = (data & 0xff);
if ((protocol == 2) && (detect_result) && (detect_work == 0))
{
HLM_slave_2streams_poll(protocol, data, 0);
}
else
break;
{
HLM_slave_1stream_poll(protocol, data, 0);
}
}
if (down_rx_work == 0)
if (detect_work == 1)
{
if ((detect_work == 1))
{
detect_work = 2;
detect_work = 2;
*tx0_txLen = (DETECT_DEVICE_PKT_TX_LEN);
*tx0_txFifo = ((DETECT_DEVICE_PKT_LEN << 20) | 1);
*tx0_txFifo = detect_pkt;
}
//*tx0_txLen = DETECT_DEVICE_PKT_TX_LEN;
i_tx0_clear_timer(0);
if ((detect_work == 2) && (HLM_RX1_FIFO_LEFT(hlm_status) >= 2))
i_tx0_txLen(DETECT_DEVICE_PKT_LEN + 4);
//*tx0_txFifo = (DETECT_DEVICE_PKT_LEN << 20) | 1;
i_tx0_txFifo(((DETECT_DEVICE_PKT_LEN << 20) | 1));
//*tx0_txFifo = detect_pkt;
i_tx0_txFifo(detect_pkt);
}
if (detect_work == 2)
{
if (HLM_RX1_FIFO_LEFT(hlm_status) >= 2)
{
uint32_t data;
uint32_t num;
uint32_t dummy;
data = *rx1_rxFifo;
num = *rx1_rxFifo;
//data = *rx1_rxFifo;
i_rx1_rxFifo(data);
//num = *rx1_rxFifo;
i_rx1_rxFifo(num);
for (i = 0; i < HLM_RX1_FIFO_LEFT(hlm_status) - 2; i++)
dummy = *rx1_rxFifo;
{
//dummy = *rx1_rxFifo;
i_rx1_rxFifo(dummy);
}
*rx1_softReset = 1;
*tx0_softReset = 1;
//*rx1_softReset = 1;
i_rx1_softReset(1);
//*tx0_softReset = 1;
i_tx0_softReset(1);
if (((data & 0xff) == 0x1) && (num == MAGIC_NUM))
detect_result = 1;
else
detect_result = 0;
detect_work = 3;
detect_work = 0;
}
if (detect_work == 0)
else
{
cur_time = read_mtimer();
if ((cur_time - stamp_time) >= DETECT_DEV_INTERVAL)
uint32_t t;
i_tx0_read_timer(t);
if (t >= 600)
{
stamp_time = cur_time;
detect_work = 1;
i_rx1_softReset(1);
i_tx0_softReset(1);
detect_work = 0;
detect_result = 0;
}
}
if ((detect_work == 3))
{
detect_work = 0;
}
if ((detect_work == 0) && (downstream_work == 0))
{
cur_time = read_mtimer();
//i_tx0_read_timer(cur_time);
if ((cur_time - stamp_time) >= DETECT_DEV_INTERVAL)
{
stamp_time = cur_time;
detect_work = 1;
}
}
}
@@ -259,3 +387,194 @@ uint32_t HLM_slave_poll(void)
}
uint32_t HLM_slave_1stream_poll(uint32_t protocol, uint32_t data, uint32_t is_crc)
{
uint32_t hlm_status;
uint32_t intflag;
uint32_t i;
uint32_t downstream_work = 1;
uint32_t upstream_work = 0;
uint32_t d_rx_index = 0;
uint32_t d_rx_pkt_len;
uint32_t u_rx_index = 0;
uint32_t u_rx_pkt_len = 0;
d_rx_pkt_len = (data >> 20) + 4;
i_tx1_txLen(d_rx_pkt_len);
i_tx1_txFifo(data);
d_rx_index++;
while (1)
{
i_hlm_status(hlm_status);
i_hlm_read_intflag(intflag);
i_hlm_clear_intflag(intflag);
for (i = 0; i < HLM_RX0_FIFO_LEFT(hlm_status); i++)
{
uint32_t data;
if (downstream_work)
{//处理下行接收
i_rx0_rxFifo(data);
d_rx_index++;
if (d_rx_pkt_len > (d_rx_index * 4))
{
i_tx1_txFifo(data);
}
else if (d_rx_pkt_len == (d_rx_index * 4))
{
i_tx1_txFifo(data);
}
else
{
downstream_work = 0;
d_rx_index = 0;
break;
}
}
else
break;
}
if (intflag & HLM_INT_TX1_END)
{
i_rx0_softReset(1);
i_tx1_softReset(1);
break;
}
}
}
#define HLM_Slave_2streams_down_poll(ds_work, index, pkt_len, intflag, status) \
do {\
if (status & HLM_RX0_VALID)\
{\
uint32_t data;\
if (ds_work)\
{/*处理下行接收*/ \
i_rx0_rxFifo(data);\
index++;\
if (pkt_len > (index))\
{\
i_tx0_txFifo(data);\
}\
else if (pkt_len == (index))\
{\
i_tx0_txFifo(data);\
}\
else\
{\
ds_work = 0;\
index = 0;\
}\
}\
}\
} while (0)
#define HLM_Slave_2streams_up_poll(us_work, index, pkt_len, intflag, status) \
do {\
if (status & HLM_RX1_VALID)\
{\
uint32_t data;\
if (us_work)\
{/*处理上行接收*/\
i_rx1_rxFifo(data);\
if (index == 0)\
{\
pkt_len = (data >> 20) + 4;\
i_tx1_txLen(pkt_len);\
pkt_len = (pkt_len >> 2);\
}\
index++;\
if (pkt_len > (index))\
{\
i_tx1_txFifo(data);\
}\
else if (pkt_len == (index))\
{\
i_tx1_txFifo(data);\
}\
else\
{\
us_work = 0;\
index = 0;\
/*is_work = 0;*/\
}\
}\
}\
} while (0)
uint32_t HLM_slave_2streams_poll(uint32_t protocol, uint32_t data, uint32_t is_crc)
{
uint32_t hlm_status;
uint32_t intflag;
uint32_t i;
uint32_t downstream_work = 1;
uint32_t upstream_work = 0;
uint32_t d_rx_index = 0;
uint32_t d_rx_pkt_len = 0;
uint32_t u_rx_index = 0;
uint32_t u_rx_pkt_len = 0;
//uint32_t is_work = 1;
d_rx_pkt_len = (data >> 20) + 4;
i_tx0_txLen(d_rx_pkt_len);
i_tx0_txFifo(data);
d_rx_pkt_len = (d_rx_pkt_len >> 2);
d_rx_index++;
while (1)
{
i_hlm_status(hlm_status);
i_hlm_read_intflag(intflag);
i_hlm_clear_intflag(intflag);
HLM_Slave_2streams_down_poll(downstream_work,
d_rx_index,
d_rx_pkt_len,
intflag,
hlm_status);
if (intflag & HLM_INT_RX1_START)
{
upstream_work = 1;
intflag = 0;
do {
i_hlm_status(hlm_status);
//i_hlm_read_intflag(intflag);
//i_hlm_clear_intflag(intflag);
HLM_Slave_2streams_down_poll(downstream_work,
d_rx_index,
d_rx_pkt_len,
intflag,
hlm_status);
HLM_Slave_2streams_up_poll(upstream_work,
u_rx_index,
u_rx_pkt_len,
intflag,
hlm_status);
} while ((upstream_work) || (downstream_work));
}
if (intflag & HLM_INT_TX1_END)
{
i_tx0_softReset(1);
i_tx1_softReset(1);
i_rx0_softReset(1);
i_rx1_softReset(1);
break;
}
}
return 0;
}

52
tb/sw/src/hlmSvrOpt.S
View File

@@ -73,7 +73,8 @@ init_func:
la x17, _rv32i_plic_handle
mv a0, x17
li x29, TL2CDR_BASE
//li x29, TL2CDR_BASE
ret
//主站启动发送数据
@@ -88,11 +89,13 @@ send_data_func:
//*tx0_txLen = 8 + tx_len; //前导+长度命令
mv x16, a2
addi x17, x16, 8
sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
i_tx0_txLen(x17)
//*tx0_txFifo = (tx_len << 20) | (0 << 16) | 0x0000;
slli x17, x16, 20
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
i_tx0_txFifo(x17)
li a0, 1
ret
@@ -131,23 +134,30 @@ slave_work_func:
#else
slave_work_func:
1:
lw x18, HLM_ReadStatus(x29)
//lw x18, HLM_ReadStatus(x29)
i_hlm_status(x18)
andi x19, x18, HLM_RX0_VALID
beqz x19, 1b
lw x20, RX0_ReadRxFifo(x29)
//lw x20, RX0_ReadRxFifo(x29)
i_rx0_rxFifo(x20)
srli x19, x20, 20
addi x19, x19, 4
sw x19, TX1_WriteTxLen(x29)
sw x20, TX1_WriteTxFifo(x29)
//sw x19, TX1_WriteTxLen(x29)
i_tx1_txLen(x29)
//sw x20, TX1_WriteTxFifo(x29)
i_tx1_txFifo(x29)
li x21, 4
1:
lw x18, HLM_ReadStatus(x29)
//lw x18, HLM_ReadStatus(x29)
i_hlm_status(x29)
andi x18, x18, HLM_RX0_VALID
beqz x18, 1b
lw x20, RX0_ReadRxFifo(x29)
sw x20, TX1_WriteTxFifo(x29)
//lw x20, RX0_ReadRxFifo(x29)
i_rx0_rxFifo(x29)
//sw x20, TX1_WriteTxFifo(x29)
i_tx1_txFifo(x29)
addi x21, x21, 4
bltu x21, x19, 1b
@@ -212,11 +222,13 @@ send_data_func:
//*tx0_txLen = 8 + tx_len; //前导+长度命令
mv x16, a2
addi x17, x16, 8
sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
i_tx0_txLen(x17)
//*tx0_txFifo = (tx_len << 20) | (0 << 16) | 0x0000;
slli x17, x16, 20
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
i_tx0_txFifo(x17)
//*tx0_txFifo = data[0]
#lw x17, 0(REG_tx_data)
@@ -256,11 +268,13 @@ exit_handle:
isr_tx0_end_hdl:
#li x17, 1
#sw x17, TX0_WriteSoftReset(REG_TL2CDR_BASE)
//i_tx0_softReset(x17)
mret
isr_tx1_end_hdl:
#li x17, 1
#sw x17, TX0_WriteSoftReset(REG_TL2CDR_BASE)
#sw x17, TX1_WriteSoftReset(REG_TL2CDR_BASE)
//i_tx1_softReset(x17)
mret
isr_rx0_err_hdl:
@@ -273,7 +287,8 @@ isr_rx0_start_hdl:
mret
isr_rx1_start_hdl:
lw x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
//lw x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
i_rx1_rxLen(x22)
sw x22, 0(REG_rx_data)
add REG_rx_data, REG_rx_data, REG_4
mret
@@ -287,7 +302,9 @@ isr_rx1_end_hdl:
isr_tx0_deq_hdl:
beqz REG_tx_data_len, 1f //if (REG_tx_data_len > 0)
lw x17, 0(REG_tx_data)
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
i_tx0_txFifo(x17)
add REG_tx_data, REG_tx_data, REG_4
sub REG_tx_data_len, REG_tx_data_len, REG_4
@@ -301,9 +318,10 @@ isr_rx0_enq_hdl:
mret
isr_rx1_enq_hdl:
lw x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
//lw x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
i_rx1_rxFifo(x17)
sw x17, 0(REG_rx_data)
add REG_rx_data, REG_rx_data, REG_4
//add REG_rx_data, REG_rx_data, REG_4
mret
isr_hdl_table:

5
tb/sw/src/plic.c
View File

@@ -1,9 +1,10 @@
#include "plic.h"
volatile uint32_t *const plic_priority = (uint32_t *)(PLIC_BASE);
volatile uint32_t *const plic_priority = (uint32_t *)(PLIC_BASE);
volatile uint32_t *const plic_pending_0_31 = (uint32_t*)( PLIC_BASE + PLIC_PENDING_0_31 );
volatile uint32_t *const plic_enable_0_31 = (uint32_t*)( PLIC_BASE + PLIC_ENABLE_0_31 );
volatile uint32_t *const plic_threshold_0 = (uint32_t*)( PLIC_BASE + PLIC_THRESHOLD_0 );
volatile uint32_t *const plic_claim = (uint32_t*)( PLIC_BASE + PLIC_CLAIM );
volatile uint32_t *const plic_claim = (uint32_t*)( PLIC_BASE + PLIC_CLAIM );
volatile uint32_t exti_isr_flag[32] = {0};

14
tb/sw/src/plic.h
View File

@@ -9,19 +9,6 @@
#define PLIC_CLAIM (0X200004U)
#define CDR_INT_TX0END 14U
#define CDR_INT_TX1END 15U
#define CDR_INT_RX0ERROR 16U
#define CDR_INT_RX1ERROR 17U
#define CDR_INT_RX0START 18U
#define CDR_INT_RX1START 19U
#define CDR_INT_RX0END 20U
#define CDR_INT_RX1END 21U
#define CDR_INT_TX0_FIFO_DEQ 22U
#define CDR_INT_TX1_FIFO_DEQ 23U
#define CDR_INT_RX0_FIFO_ENQ 24U
#define CDR_INT_RX1_FIFO_ENQ 25U
#ifndef __ASSEMBLER__
#include "stdint.h"
@@ -32,6 +19,7 @@ extern volatile uint32_t *const plic_enable_0_31;
extern volatile uint32_t *const plic_threshold_0;
extern volatile uint32_t *const plic_claim;
extern volatile uint32_t exti_isr_flag[32];
#endif

19
tb/sw/src/startup.S
View File

@@ -1,4 +1,5 @@
#include "tl2cdr.h"
#include "system_cfg.h"
.extern main
@@ -50,7 +51,10 @@ _prog_start:
li x31, 0
#endif
li sp, 0x40011000
//li sp, 0x40011000
li t0, STACK_SIZE
la sp, sys_stack
add sp, sp, t0
#ifdef __riscv_i
la t0, trap_entry
@@ -66,7 +70,7 @@ _prog_start:
mv t0, a0 #这里选择不同的trap_entry服务函数,这个是RV32I的代码
#endif
csrw mtvec, t0
li t0, 1 << 11
li t0, (1 << 11) //| (1 << 13) //13bit是rocc的中断
csrw mie, t0
csrr t0, mstatus
@@ -124,8 +128,9 @@ opt_trap_entry:
#sw t6,124(sp)
csrr t2, mcause
li s0, 0x80000000
and s0, t2, s0
//li s0, 0x80000000
//and s0, t2, s0
srli s0, t2, 31
1: beqz s0, 1b #这个是异常,死循环查问题吧
andi s0, t2, 0xf
la t2, isr_j_table
@@ -161,6 +166,10 @@ exti_isr:
#lw sp,8(sp)
#lw gp,12(sp)
#lw tp,16(sp)
rocc_isr:
//add rocc interrupt here
i_hlm_read_intflag(t0)
i_hlm_clear_intflag(t0)
exit_isr:
lw t0,20(sp)
@@ -209,7 +218,7 @@ isr_j_table:
1: j 1b # a jump to unknown_isr
j exti_isr # b jump to exti_isr
1: j 1b # c jump to unknown_isr
1: j 1b # d jump to unknown_isr
j rocc_isr # d jump to unknown_isr
1: j 1b # e jump to unknown_isr
1: j 1b # f jump to unknown_isr
#endif

2
tb/sw/src/system_cfg.h
View File

@@ -6,4 +6,6 @@
#define RX_BUF_NUM 1
#define RX_BUF_MAX_LEN 1024
#define STACK_SIZE (1024 * 8)
#endif

386
tb/sw/src/view_signal.tcl Normal file
View File

@@ -0,0 +1,386 @@
#package require gtkwave
proc addSeparator {name} {
gtkwave::/Edit/Insert_Comment "----$name----" 0
#gtkwave::/Edit/Insert_Blank
}
proc add_signals {siglist filter1 color1 filter2 color2 } {
set fw1 $filter1
set fw2 $filter2
foreach v $siglist {
set i1 [ string first $fw1 $v ]
set i2 [ string first $fw2 $v ]
set i3 [ string first "#" $v ]
#puts stderr "sig: $v $i1 $i2 $i3"
if {$i1 != -1 && $i3 == -1} {
gtkwave::addSignalsFromList $v
gtkwave::/Edit/Color_Format/$color1
gtkwave::/Edit/UnHighlight_All
} elseif {$i2 != -1 && $i3 == -1} {
gtkwave::addSignalsFromList $v
gtkwave::/Edit/Color_Format/$color2
gtkwave::/Edit/UnHighlight_All
} elseif {$i3 != -1} {
#puts stderr "sig: $v ignore"
} else {
gtkwave::addSignalsFromList $v
gtkwave::/Edit/Color_Format/Green
gtkwave::/Edit/UnHighlight_All
}
}
}
proc uadd_signals {siglist f_c_list } {
foreach v $siglist {
set idx0 [ string first "#" $v ]
set has_been_add 0
dict for {filter color} $f_c_list {
set idx1 [ string first $filter $v ]
#puts stderr "sig: $v $i1 $i2 $i3"
if {$idx0 != -1} {
set has_been_add 1
break
} elseif {$idx1 != -1} {
gtkwave::addSignalsFromList $v
gtkwave::/Edit/Color_Format/$color
gtkwave::/Edit/UnHighlight_All
set has_been_add 1
break
} else {
#continue
#gtkwave::addSignalsFromList $v
#gtkwave::/Edit/Color_Format/Green
#gtkwave::/Edit/UnHighlight_All
}
}
if {$has_been_add == 0} {
gtkwave::addSignalsFromList $v
gtkwave::/Edit/Color_Format/Green
gtkwave::/Edit/UnHighlight_All
}
}
}
# 信号列表（使用完整层次路径）
set mst_signals {
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
}
set mst_signals_ext {
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_ready
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_valid
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_reset
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_ready
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_valid
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_reset
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_ready
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_valid
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_reset
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_ready
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_valid
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_reset
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_0
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_1
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_0
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_1
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_0
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_1
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_0
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_1
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_bits[31:0]
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_ready
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_valid
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_bits[31:0]
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_ready
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_valid
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_ready
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_valid
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_ready
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_valid
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_ready
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_valid
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_ready
TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_valid
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_bits[31:0]
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_ready
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_valid
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_bits[31:0]
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_ready
#TOP.SimTop.s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_valid
}
set slv0_signals {
#TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
}
set slv0_signals_ext {
#TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
#TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
#TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
#TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
#TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_reset
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_reset
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_reset
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_reset
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_0
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_1
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_0
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_1
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_0
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_1
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_0
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_1
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_valid
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_ready
TOP.SimTop.s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_valid
}
set slv1_signals {
#TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
}
set slv1_signals_ext {
#TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
#TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
#TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
#TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
#TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_reset
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_reset
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_reset
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_reset
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_0
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_1
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_0
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_1
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_0
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_1
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_0
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_1
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_valid
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_ready
TOP.SimTop.s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_valid
}
set slv2_signals {
#TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
}
set slv2_signals_ext {
#TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_clock
#TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_0_io_serDat
#TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_serDat
#TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRin_1_io_serDat
#TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_serDat
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_io_axis_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_0_reset
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_io_axis_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDRIn_1_reset
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_io_axis_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_0_reset
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_io_axis_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_CDROut_1_reset
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_0
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intRxEnd_1
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_0
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intRxError_1
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_0
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intRxStart_1
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_0
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_intTxEnd_1
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_deq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_0_io_enq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_deq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_0_io_enq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_deq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_rxFifo_1_io_enq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_deq_valid
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_bits[31:0]
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_ready
TOP.SimTop.s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.roccs_txFifo_1_io_enq_valid
}
set filter_color_list [dict create "_bits" Blue "_int" Red "_0_io" Yellow "_1_io" Orange]
set ft1 "_0_io"
set ft2 "_1_io"
set c1 Indigo
set c2 Orange
# 添加信号到波形窗口
addSeparator "main station"
#gtkwave::addSignalsFromList $mst_signals
#add_signals $mst_signals $ft1 $c1 $ft2 $c2
uadd_signals $mst_signals $filter_color_list
addSeparator "Slave 0"
#gtkwave::addSignalsFromList $slv0_signals
#add_signals $slv0_signals $ft1 $c1 $ft2 $c2
uadd_signals $slv0_signals $filter_color_list
addSeparator "Slave 1"
#gtkwave::addSignalsFromList $slv1_signals
#add_signals $slv1_signals $ft1 $c1 $ft2 $c2
uadd_signals $slv1_signals $filter_color_list
addSeparator "Slave 2"
#gtkwave::addSignalsFromList $slv2_signals
#add_signals $slv2_signals $ft1 $c1 $ft2 $c2
uadd_signals $slv2_signals $filter_color_list
addSeparator "main station"
#gtkwave::addSignalsFromList $mst_signals_ext
#add_signals $mst_signals_ext $ft1 $c1 $ft2 $c2
uadd_signals $mst_signals_ext $filter_color_list
addSeparator "Slave 0"
#gtkwave::addSignalsFromList $slv0_signals_ext
#add_signals $slv0_signals_ext $ft1 $c1 $ft2 $c2
uadd_signals $slv0_signals_ext $filter_color_list
addSeparator "Slave 1"
#gtkwave::addSignalsFromList $slv1_signals_ext
#add_signals $slv1_signals_ext $ft1 $c1 $ft2 $c2
uadd_signals $slv1_signals_ext $filter_color_list
addSeparator "Slave 2"
#gtkwave::addSignalsFromList $slv2_signals_ext
#add_signals $slv2_signals_ext $ft1 $c1 $ft2 $c2
uadd_signals $slv2_signals_ext $filter_color_list
# 设置显示范围
gtkwave::/Time/Zoom/Zoom_Full
# 高亮关键信号
#gtkwave::highlightSignalsFromList {top.reset_n top.clk}