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将代码参数化,便于代码自动化生成

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bacon
2025-08-16 18:38:50 +08:00
parent 573a1ad45f
commit be792e000a
1 changed files with 87 additions and 59 deletions
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146
tb/shinTest/ShinTopSpiTb.v
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@@ -40,17 +40,37 @@ module ShinTopSpiTb(
reg [15:0] multiCLK;
wire [3:0] dDat_w;
wire [3:0] uDat_w;
`define DEV_NUM 4 //slave num
`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master
`define SPI_CSN_NUM (`ALL_DEV_NUM * 3)
`define HW_SERIAL 0 //(48'h4c5850303031)
`define IQSPI_PINS(N) (`N*4+3):(`N*4)
`define EQSPI_PINS(N) ((`N + `ALL_DEV_NUM)*4+3):((`N + `ALL_DEV_NUM)*4)
`define IQSPI_MISO(N) qspi_miso[`IQSPI_PINS(`N)]
`define EQSPI_MISO(N) qspi_miso[`EQSPI_PINS(`N)]
`define IQSPI_CSN_NUM(id) (`id)
`define ESPI_CSN_NUM(id) ((`id)+(`ALL_DEV_NUM))
`define EQSPI_CSN_NUM(id) ((`id)+(`ALL_DEV_NUM)*2)
`define IQSPI_CSN(id) spi_csn[`IQSPI_CSN_NUM(`id)]
`define ESPI_CSN(id) spi_csn[`ESPI_CSN_NUM(`id)]
`define EQSPI_CSN(id) spi_csn[`EQSPI_CSN_NUM(`id)]
wire [(`DEV_NUM - 1):0] dDat_w;
wire [(`DEV_NUM - 1):0] uDat_w;
wire spi_sck;
wire spi_mosi;
wire [4:0] spi_miso;
reg [14:0] spi_csn;
reg [(`SPI_CSN_NUM - 1):0] spi_csn;
wire qspi_sck;
wire [3:0] qspi_mosi;
wire [40-1:0] qspi_miso;
//wire [40-1:0] qspi_miso;
wire [(`ALL_DEV_NUM * 4 * 2 - 1):0] qspi_miso;
integer spidata_file;
integer c_line;
@@ -61,9 +81,9 @@ module ShinTopSpiTb(
reg [63:0] _temp_time;
reg _reset_deactive;
wire [4:0] isSoftReset;
wire [(`ALL_DEV_NUM - 1):0] isSoftReset;
wire [4:0] io_int_sig;
wire [`DEV_NUM:0] io_int_sig;
reg latch0;
reg latch1;
@@ -96,27 +116,27 @@ ShinTop s_ShinTop_Mst(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso[3:0]),
.io_iqspi_miso(`IQSPI_MISO(0)),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[0]),
.io_iqspi_csn(`IQSPI_CSN(0)),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[0]),
.io_ospi_csn (spi_csn[5]),
.io_ospi_csn (`ESPI_CSN(0)),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso[4*5+3:4*5]),
.io_oqspi_miso(`EQSPI_MISO(0)),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[10]),
.io_oqspi_csn(`EQSPI_CSN(0)),
.io_isSoftReset(isSoftReset[0]),
.io_interrupt(io_int_sig[0]),
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(0),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
);
@@ -148,26 +168,26 @@ ShinTop s_ShinTop_slv0(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso[4*1+3:4*1]),
.io_iqspi_miso(`IQSPI_MISO(1)),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[1]),
.io_iqspi_csn(`IQSPI_CSN(1)),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[1]),
.io_ospi_csn (spi_csn[6]),
.io_ospi_csn (`ESPI_CSN(1)),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso[4*6+3:4*6]),
.io_oqspi_miso(`EQSPI_MISO(1)),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[11]),
.io_oqspi_csn(`EQSPI_CSN(1)),
.io_isSoftReset(isSoftReset[1]),
.io_interrupt(io_int_sig[1]),
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(0),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
);
@@ -199,26 +219,26 @@ ShinTop s_ShinTop_slv1(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso[4*2+3:4*2]),
.io_iqspi_miso(`IQSPI_MISO(2)),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[2]),
.io_iqspi_csn(`IQSPI_CSN(2)),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[2]),
.io_ospi_csn (spi_csn[7]),
.io_ospi_csn (`ESPI_CSN(2)),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso[4*7+3:4*7]),
.io_oqspi_miso(`EQSPI_MISO(2)),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[12]),
.io_oqspi_csn(`EQSPI_CSN(2)),
.io_isSoftReset(isSoftReset[2]),
.io_interrupt(io_int_sig[2]),
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(0),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
);
@@ -250,26 +270,26 @@ ShinTop s_ShinTop_slv2(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso[4*3+3:4*3]),
.io_iqspi_miso(`IQSPI_MISO(3)),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[3]),
.io_iqspi_csn(`IQSPI_CSN(3)),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[3]),
.io_ospi_csn (spi_csn[8]),
.io_ospi_csn (`ESPI_CSN(3)),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso[4*8+3:4*8]),
.io_oqspi_miso(`EQSPI_MISO(3)),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[13]),
.io_oqspi_csn(`EQSPI_CSN(3)),
.io_isSoftReset(isSoftReset[3]),
.io_interrupt(io_int_sig[3]),
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(0),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
);
@@ -301,37 +321,30 @@ ShinTop s_ShinTop_slv3(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso[4*4+3:4*4]),
.io_iqspi_miso(`IQSPI_MISO(4)),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[4]),
.io_iqspi_csn(`IQSPI_CSN(4)),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso[4]),
.io_ospi_csn (spi_csn[9]),
.io_ospi_csn (`ESPI_CSN(4)),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso[4*9+3:4*9]),
.io_oqspi_miso(`EQSPI_MISO(4)),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[14]),
.io_oqspi_csn(`EQSPI_CSN(4)),
.io_isSoftReset(isSoftReset[4]),
.io_interrupt(io_int_sig[4]),
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(0),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
);
initial begin
clock = 0;
clk8x = 0;
@@ -344,7 +357,7 @@ initial begin
$timeformat(-9, 2, " ns", 8);
spi_csn = ~15'b0;
spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0;
#100
reset <= 1;
@@ -426,23 +439,38 @@ end
assign qspi_mosi = exChangeRego[7:4];
wire [3:0] qspi_mux_miso =
( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) |
( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) |
( qspi_miso[4*2+3:4*2] & ~{4{spi_csn[ 2]}}) |
( qspi_miso[4*3+3:4*3] & ~{4{spi_csn[ 3]}}) |
( qspi_miso[4*4+3:4*4] & ~{4{spi_csn[ 4]}}) |
( qspi_miso[4*5+3:4*5] & ~{4{spi_csn[10]}}) |
( qspi_miso[4*6+3:4*6] & ~{4{spi_csn[11]}}) |
( qspi_miso[4*7+3:4*7] & ~{4{spi_csn[12]}}) |
( qspi_miso[4*8+3:4*8] & ~{4{spi_csn[13]}}) |
( qspi_miso[4*9+3:4*9] & ~{4{spi_csn[14]}});
//( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) |
//( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) |
//( qspi_miso[4*2+3:4*2] & ~{4{spi_csn[ 2]}}) |
//( qspi_miso[4*3+3:4*3] & ~{4{spi_csn[ 3]}}) |
//( qspi_miso[4*4+3:4*4] & ~{4{spi_csn[ 4]}}) |
//( qspi_miso[4*5+3:4*5] & ~{4{spi_csn[10]}}) |
//( qspi_miso[4*6+3:4*6] & ~{4{spi_csn[11]}}) |
//( qspi_miso[4*7+3:4*7] & ~{4{spi_csn[12]}}) |
//( qspi_miso[4*8+3:4*8] & ~{4{spi_csn[13]}}) |
//( qspi_miso[4*9+3:4*9] & ~{4{spi_csn[14]}});
(`IQSPI_MISO(0) & ~{4{`IQSPI_CSN(0)}}) |
(`IQSPI_MISO(1) & ~{4{`IQSPI_CSN(1)}}) |
(`IQSPI_MISO(2) & ~{4{`IQSPI_CSN(2)}}) |
(`IQSPI_MISO(3) & ~{4{`IQSPI_CSN(3)}}) |
(`IQSPI_MISO(4) & ~{4{`IQSPI_CSN(4)}}) |
(`EQSPI_MISO(0) & ~{4{`EQSPI_CSN(0)}}) |
(`EQSPI_MISO(1) & ~{4{`EQSPI_CSN(1)}}) |
(`EQSPI_MISO(2) & ~{4{`EQSPI_CSN(2)}}) |
(`EQSPI_MISO(3) & ~{4{`EQSPI_CSN(3)}}) |
(`EQSPI_MISO(4) & ~{4{`EQSPI_CSN(4)}});
wire spi_mux_miso =
( spi_miso[0] & ~spi_csn[5] ) |
( spi_miso[1] & ~spi_csn[6] ) |
( spi_miso[2] & ~spi_csn[7] ) |
( spi_miso[3] & ~spi_csn[8] ) |
( spi_miso[4] & ~spi_csn[9] );
//( spi_miso[0] & ~spi_csn[5] ) |
//( spi_miso[1] & ~spi_csn[6] ) |
//( spi_miso[2] & ~spi_csn[7] ) |
//( spi_miso[3] & ~spi_csn[8] ) |
//( spi_miso[4] & ~spi_csn[9] );
( spi_miso[0] & ~`ESPI_CSN(0)) |
( spi_miso[1] & ~`ESPI_CSN(1)) |
( spi_miso[2] & ~`ESPI_CSN(2)) |
( spi_miso[3] & ~`ESPI_CSN(3)) |
( spi_miso[4] & ~`ESPI_CSN(4));
reg isReq = 0;
reg isBusy = 0;