From 79f29a1d7e5c64311c5df9b4b38213b029db7bcd Mon Sep 17 00:00:00 2001 From: bacon Date: Mon, 25 Aug 2025 17:49:40 +0800 Subject: [PATCH 01/11] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E8=87=AA=E5=8A=A8?= =?UTF-8?q?=E6=B7=BB=E5=8A=A0=E4=BB=8E=E7=AB=99=E8=AE=BE=E5=A4=87=E7=9A=84?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 17 +++++++++-------- tb/shinTest/gen_pkt.py | 20 ++++++++++---------- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 451d2cc..5eebe58 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -523,8 +523,9 @@ always @(posedge clock) begin end end - -wire isQspi = (idx >= 0 && idx <= 4) || idx >= 10; +//DEV_NUM +//ALL_DEV_NUM +wire isQspi = (idx >= 0 && idx <= (`ALL_DEV_NUM - 1)) || idx >= (`ALL_DEV_NUM * 2); wire [11:0] nextByteCnt = byteCnt + 1; //输出 @@ -594,7 +595,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in begin //$fwrite(spidata_file, "------------%5t------------\n", $realtime); $fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n", - $realtime, ((sidx >= 5)? ((sidx >= 10)? (sidx - 10):(sidx - 5)):sidx), txBuf[0], txBuf[1], + $realtime, ((sidx >= `ALL_DEV_NUM)? ((sidx >= (`ALL_DEV_NUM * 2))? (sidx - (`ALL_DEV_NUM * 2)):(sidx - `ALL_DEV_NUM)):sidx), txBuf[0], txBuf[1], ((txBuf[2] == 0)? "Write":" Read"), slength); if ( ((saddress == 16'h0800) @@ -605,7 +606,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in || (saddress == 16'h3000) || (saddress == 16'h3800) || (saddress == 16'h4000)) - && ((sidx == 0) || (sidx == 5) || (sidx == 10))) begin + && ((sidx == 0) || (sidx == `ALL_DEV_NUM) || (sidx == (`ALL_DEV_NUM * 2)))) begin _pos = 3; for (integer _k = 0; _k < 4; _k++) begin if (scmd == 0) begin @@ -771,8 +772,8 @@ end `define INTERFACE_IDX 0 //internal spi `define IF_IDX(idx) ((`INTERFACE_IDX)+(idx)) `define IF_IQSPI(idx) ((idx)) -`define IF_OQSPI(idx) ((10) + (idx)) -`define IF_OSPI(idx) ((5) + (idx)) +`define IF_OQSPI(idx) ((`ALL_DEV_NUM * 2) + (idx)) +`define IF_OSPI(idx) ((`ALL_DEV_NUM) + (idx)) `define SPI_WRITE 8'h0 `define SPI_READ 8'h1 @@ -944,7 +945,7 @@ initial begin `endif begin:SETTING_INTERFACE - if ((`INTERFACE_IDX) == 5) begin + if ((`INTERFACE_IDX) == `ALL_DEV_NUM) begin $fdisplay(spidata_file, "\n\n从内部QSPI配置使用外部的SPI接口访问EasyBus"); txBuf[0+3] = 8'h01; spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(0)) ); @@ -952,7 +953,7 @@ initial begin spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(2)) ); spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(3)) ); spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(4)) ); - end else if ((`INTERFACE_IDX) == 10) begin + end else if ((`INTERFACE_IDX) == (`ALL_DEV_NUM * 2)) begin $fdisplay(spidata_file, "\n\n从内部QSPI配置使用外部的QSPI接口访问EasyBus"); txBuf[0+3] = 8'h02; spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(0)) ); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 37f91dd..205764e 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -4,7 +4,7 @@ from pyutils import * from testcase import environment, readregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac if __name__ == '__main__': - environment.gen_slv_dev_num(4) + environment.gen_slv_dev_num(10) environment.bringup() #add_tc_2_runlist(errorPkt.tc1()) #add_tc_2_runlist(errorPkt.tc2()) @@ -14,8 +14,8 @@ if __name__ == '__main__': #add_tc_2_runlist(errorPkt.tc6()) add_tc_2_runlist(base.tc1()) - add_tc_2_runlist(base.tc2()) - add_tc_2_runlist(base.tc3()) + #add_tc_2_runlist(base.tc2()) + #add_tc_2_runlist(base.tc3()) #add_tc_2_runlist(base.tc4()) #add_tc_2_runlist(base.tc5()) #add_tc_2_runlist(base.tc6()) @@ -79,13 +79,13 @@ if __name__ == '__main__': #add_tc_2_runlist(watchdog.tc1()) #add_tc_2_runlist(watchdog.tc2()) - add_tc_2_runlist(mac.tc1()) - add_tc_2_runlist(mac.tc2()) - add_tc_2_runlist(mac.tc3()) - add_tc_2_runlist(mac.tc4()) - add_tc_2_runlist(mac.tc5()) - add_tc_2_runlist(mac.tc6()) - add_tc_2_runlist(mac.tc7()) + #add_tc_2_runlist(mac.tc1()) + #add_tc_2_runlist(mac.tc2()) + #add_tc_2_runlist(mac.tc3()) + #add_tc_2_runlist(mac.tc4()) + #add_tc_2_runlist(mac.tc5()) + #add_tc_2_runlist(mac.tc6()) + #add_tc_2_runlist(mac.tc7()) environment.teardown() From 6f1101f6dcaacf82eda4c426f5ce85344261bcef Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 25 Aug 2025 19:16:27 +0800 Subject: [PATCH 02/11] =?UTF-8?q?=E6=94=B9=E5=BC=82=E6=AD=A5=E5=A4=8D?= =?UTF-8?q?=E4=BD=8D=EF=BC=8C=E5=A2=9E=E5=8A=A0flush=E6=8E=A5=E5=8F=A3?= =?UTF-8?q?=EF=BC=8C=E5=88=A0=E9=99=A4=E5=85=B6=E4=BB=96=E5=B7=A5=E7=A8=8B?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E4=BB=A5=E7=BC=96=E8=AF=91=E9=80=9A=E8=BF=87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- build.sbt | 2 - src/main/scala/Switch/DMA.scala | 175 ---- src/main/scala/Switch/DMARegisters.scala | 133 --- src/main/scala/Switch/MAC.scala | 468 --------- src/main/scala/Switch/MacRegisters.scala | 349 ------- src/main/scala/Switch/Parameters.scala | 41 - src/main/scala/Switch/PiPoBuff.scala | 175 ---- src/main/scala/Switch/Robin.scala | 70 -- src/main/scala/Switch/Switch.scala | 174 ---- src/main/scala/Switch/SwitchMux.scala.bk | 159 --- src/main/scala/Switch/SwitchNode.scala | 62 -- src/main/scala/Switch/WithSwitch.scala | 49 - src/main/scala/Switch/mac/MII.scala | 239 ----- src/main/scala/Switch/mac/MacBundle.scala | 78 -- src/main/scala/Switch/mac/MacFifo.scala | 77 -- src/main/scala/Switch/mac/MacRx.scala | 298 ------ src/main/scala/Switch/mac/MacSRAM.scala | 58 -- src/main/scala/Switch/mac/MacStatus.scala | 128 --- src/main/scala/Switch/mac/MacTileLinkRx.scala | 232 ----- src/main/scala/Switch/mac/MacTileLinkTx.scala | 238 ----- src/main/scala/Switch/mac/MacTx.scala | 399 -------- src/main/scala/Wrapper/Efabless.scala | 136 --- src/main/scala/backBoard/ebus/CDRIn.scala | 100 +- src/main/scala/backBoard/ebus/CDROut.scala | 23 +- .../{RoCC2CDR.scala => RoCC2CDR.scala.bk} | 0 .../ebus/{TL2CDR.scala => TL2CDR.scala.bk} | 912 +++++++++--------- src/main/scala/backBoard/ebus/crc32.scala | 78 +- src/main/scala/backBoard/shin/Interface.scala | 2 +- .../scala/backBoard/shin/MasterParser.scala | 6 +- src/main/scala/backBoard/shin/SMUnit.scala | 19 +- src/main/scala/backBoard/shin/ShinTop.scala | 12 +- .../scala/backBoard/shin/SlaveParser.scala | 10 +- .../scala/backBoard/shin/SlaveRecParser.scala | 68 +- .../scala/backBoard/shin/SlaveSendGen.scala | 55 +- .../scala/backBoard/shin/SpiInterface.scala | 2 +- src/test/scala/gcd/test.scala | 6 +- 36 files changed, 615 insertions(+), 4418 deletions(-) delete mode 100644 src/main/scala/Switch/DMA.scala delete mode 100644 src/main/scala/Switch/DMARegisters.scala delete mode 100644 src/main/scala/Switch/MAC.scala delete mode 100644 src/main/scala/Switch/MacRegisters.scala delete mode 100644 src/main/scala/Switch/Parameters.scala delete mode 100644 src/main/scala/Switch/PiPoBuff.scala delete mode 100644 src/main/scala/Switch/Robin.scala delete mode 100644 src/main/scala/Switch/Switch.scala delete mode 100644 src/main/scala/Switch/SwitchMux.scala.bk delete mode 100644 src/main/scala/Switch/SwitchNode.scala delete mode 100644 src/main/scala/Switch/WithSwitch.scala delete mode 100644 src/main/scala/Switch/mac/MII.scala delete mode 100644 src/main/scala/Switch/mac/MacBundle.scala delete mode 100644 src/main/scala/Switch/mac/MacFifo.scala delete mode 100644 src/main/scala/Switch/mac/MacRx.scala delete mode 100644 src/main/scala/Switch/mac/MacSRAM.scala delete mode 100644 src/main/scala/Switch/mac/MacStatus.scala delete mode 100644 src/main/scala/Switch/mac/MacTileLinkRx.scala delete mode 100644 src/main/scala/Switch/mac/MacTileLinkTx.scala delete mode 100644 src/main/scala/Switch/mac/MacTx.scala delete mode 100644 src/main/scala/Wrapper/Efabless.scala rename src/main/scala/backBoard/ebus/{RoCC2CDR.scala => RoCC2CDR.scala.bk} (100%) rename src/main/scala/backBoard/ebus/{TL2CDR.scala => TL2CDR.scala.bk} (97%) diff --git a/build.sbt b/build.sbt index 91f86f0..820ff71 100644 --- a/build.sbt +++ b/build.sbt @@ -114,8 +114,6 @@ lazy val blocks = (project in file("./rocket-chip-blocks")) lazy val root = (project in file(".")) - .dependsOn(rocketchip) - .dependsOn(blocks) .settings( name := "%NAME%", libraryDependencies ++= Seq( diff --git a/src/main/scala/Switch/DMA.scala b/src/main/scala/Switch/DMA.scala deleted file mode 100644 index de6ca8c..0000000 --- a/src/main/scala/Switch/DMA.scala +++ /dev/null @@ -1,175 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.tilelink._ - - -abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchNode{ - class MacTileLinkMasterIO extends Bundle{ - val A = Decoupled(new TLBundleA(edgeOut.bundle)) - val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle))) - } - - class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{ - val dmaMst = new MacTileLinkMasterIO - - val cfg = Vec( chn, Flipped(new DMA_Register_Bundle) ) - - val selIn = Input(UInt( (log2Ceil(chn)).W)) - val selOut = Output(UInt((log2Ceil(chn)).W)) - - } - - val io: SwitchMuxIO = IO(new SwitchMuxIO) - val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D) - - val rxBuff = Module(new RxBuff(8)) - val txBuff = Module(new TxBuff(0)) - - - - def stateIdle = 0.U - def stateRx = 1.U - def stateTx = 2.U - - val stateNxt = Wire(UInt(2.W)) - val stateCur = RegNext(stateNxt, stateIdle) - val stateDMA = RegInit(0.U(2.W)) - - val dmaAValid = RegInit(false.B) - val dmaABits = Reg(new TLBundleA(edgeOut.bundle)) - val dmaAddress = Reg( UInt(32.W) ) - - val trigRxNum = Reg(UInt((log2Ceil(chn)).W)) - val trigTxNum = Reg(UInt((log2Ceil(chn)).W)) - - val rxLength = RegInit(0.U) -} - -trait DMAMstFSM{ this: DMAMstBase => - - stateNxt := - Mux1H(Seq( - ( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( txBuff.io.deq.valid, stateRx, stateIdle ) ), - ( stateCur === stateRx ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ), - ( stateCur === stateTx ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ), - )) - - - when( stateNxt =/= stateIdle && stateCur === stateIdle ){ - stateDMA := 1.U - } .elsewhen( io.dmaMst.A.fire ){ - stateDMA := 2.U - } .elsewhen( io.dmaMst.D.fire & isLastD ){ - when( stateCur === stateTx & dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen) ){ - stateDMA := 0.U - } .elsewhen( stateCur === stateRx & ~txBuff.io.deq.valid ){ - stateDMA := 0.U - } .otherwise{ - stateDMA := 1.U - } - } - -} - - -trait DMAMstTileLink{ this: DMAMstBase => - - - - val mInfoValid = stateCur === stateTx - - when( txBuff.io.deq.valid & stateCur === stateIdle & stateNxt === stateRx ){ - - trigRxNum := io.selIn - - dmaAddress := io.cfg(io.selIn).r_RxPtr - } - - for( i <- 0 until chn ){ - io.cfg(i).triRx := txBuff.io.deq.fire & txBuff.io.deq.bits.isLast & trigRxNum === i.U - io.cfg(i).r_RxLen := RegEnable( rxLength + 1.U, io.cfg(i).triRx ) - } - - for( i <- 0 until chn ){ - when( io.cfg(i).triTx & io.cfg(i).r_TxLen > 32.U & stateCur === stateIdle ){ - trigTxNum := i.U - dmaAddress := io.cfg(i).r_TxPtr - assert( stateNxt === stateTx ) - } - } - - when( io.dmaMst.A.fire ){ - dmaAddress := dmaAddress + 1.U - } - - txBuff.io.deq.ready := io.dmaMst.A.fire & (stateCur === stateRx) - assert( ~(txBuff.io.deq.ready & ~txBuff.io.deq.valid) ) - - when( io.dmaMst.A.fire ){ - dmaAValid := false.B - }.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){ - dmaAValid := true.B - dmaABits := - edgeOut.Get( - fromSource = 0.U, - toAddress = dmaAddress, - lgSize = log2Ceil(8/8).U, - )._2 - } .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) { - dmaAValid := true.B - dmaABits := - edgeOut.Put( - fromSource = 0.U, - toAddress = dmaAddress, - lgSize = log2Ceil(8/8).U, - data = txBuff.io.deq.bits.data, - mask = "b1".U, - )._2 - } - - - io.dmaMst.A.valid := dmaAValid - io.dmaMst.A.bits := dmaABits - - - io.dmaMst.D.ready := - Mux1H(Seq( - ( stateCur === stateRx ) -> true.B, - ( stateCur === stateTx ) -> rxBuff.io.enq.ready, - )) -} - -trait DMAMstBuff{ this: DMAMstBase => - - - - when( txBuff.io.deq.fire ){ - when( txBuff.io.deq.bits.isStart ){ - rxLength := 0.U - } .otherwise{ - rxLength := rxLength + 1.U - } - } - - - - - rxBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx - rxBuff.io.enq.bits.data := io.dmaMst.D.bits.data - rxBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.cfg(trigTxNum).r_TxPtr, io.dmaMst.A.fire) - rxBuff.io.enq.bits.isLast := dmaAddress === (io.cfg(trigTxNum).r_TxPtr + io.cfg(trigTxNum).r_TxLen) - - io.selOut := trigTxNum - -} - - -abstract class DMAMst(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMstBase(edgeOut) -with DMAMstFSM -with DMAMstTileLink -with DMAMstBuff diff --git a/src/main/scala/Switch/DMARegisters.scala b/src/main/scala/Switch/DMARegisters.scala deleted file mode 100644 index 03f58d2..0000000 --- a/src/main/scala/Switch/DMARegisters.scala +++ /dev/null @@ -1,133 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ - - -class DMA_Register_Bundle extends Bundle{ - val r_TxPtr = Output(UInt(32.W)) - val r_RxPtr = Output(UInt(32.W)) - val r_TxLen = Output(UInt(16.W)) - val r_RxLen = Input (UInt(16.W)) - val triTx = Output( Bool()) - val triRx = Input ( Bool()) -} - - -class DmaRegIO(implicit p: Parameters) extends SwitchBundle{ - - val MacAddr = Output(UInt(48.W)) - - val cfg = Vec( chn, new DMA_Register_Bundle ) -} - -class DmaReg(implicit p: Parameters) extends LazyModule with HasSwitchParameters{ - - - - - - // DTS - val dtsdevice = new SimpleDevice("dma",Seq("dma_0")) - - - val configNode = TLRegisterNode( - address = Seq(AddressSet(0x30001000L, 0x00000fffL)), - device = dtsdevice, - concurrency = 1, - beatBytes = 32/8, - executable = true - ) - lazy val module = new DmaRegImp(this) -} - -class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{ - - val io: DmaRegIO = IO(new DmaRegIO) - - - - - - - val txPtr = for( i <- 0 until chn ) yield { RegInit( "h80002000".U(32.W)) } - val rxPtr = for( i <- 0 until chn ) yield { RegInit( "h80002000".U(32.W)) } - val txLen = for( i <- 0 until chn ) yield { RegInit( 65535.U(16.W)) } - // val rxLen = RegInit( 65535.U(16.W)) - val triRx = for( i <- 0 until chn ) yield { RegInit(false.B) } - - for( i <- 0 until chn ) { - io.cfg(i).r_TxPtr := txPtr(i) - io.cfg(i).r_RxPtr := rxPtr(i) - io.cfg(i).r_TxLen := txLen(i) - } - - for( i <- 0 until chn ) { when( io.cfg(i).triRx ) { triRx(i) := true.B } } - - - - - val comMap = Seq( - ( 0 << 2 ) -> - RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( - RegField(32) - )), - - ( 1 << 2 ) -> - RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( - RegField(32) - )) - ) - - val trigMap = - ((0 until chn).map{ i => - ( (10*i + 10) << 2 ) -> - RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq( - RegField.w(1, RegWriteFn((valid, data) => { io.cfg(i).triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))), - RegField(1, triRx(i), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))) - )) - }) - - val lenMap = - (0 until chn).map{ i => - ( (10*i + 11) << 2 ) -> - RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq( - RegField(16, txLen(i), RegFieldDesc("txLen", "length of tx", reset=Some(65535))), - RegField.r(16, io.cfg(i).r_RxLen, RegFieldDesc("rxLen", "length of rx")), - )) - } - - val txAddrMap = - (0 until chn).map{ i => - ( (10*i + 12) << 2 ) -> - RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq( - RegField(32, txPtr(i), RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))), - )) - } - - val rxAddrMap = - (0 until chn).map{ i => - ( (10*i + 13) << 2 ) -> - RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq( - RegField(32, rxPtr(i), RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))), - )) - } - - - val regMap = comMap ++ trigMap ++ lenMap ++ txAddrMap ++ rxAddrMap - outer.configNode.regmap(regMap: _*) - - - - - - -} - - diff --git a/src/main/scala/Switch/MAC.scala b/src/main/scala/Switch/MAC.scala deleted file mode 100644 index cc1b5c6..0000000 --- a/src/main/scala/Switch/MAC.scala +++ /dev/null @@ -1,468 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ - -import MAC._ - - - - -class MII extends Bundle with MDIO{ - // Tx - val mtx_clk_pad_i = Input(Bool()) - val mtxd_pad_o = Output(UInt(4.W)) - val mtxen_pad_o = Output(Bool()) - - // Rx - val mrx_clk_pad_i = Input(Bool()) - val mrxd_pad_i = Input(UInt(4.W)) - val mrxdv_pad_i = Input(Bool()) - - // Common Tx and Rx - val mcoll_pad_i = Input(Bool()) - val mcrs_pad_i = Input(Bool()) -} - - - -class MacIO extends Bundle{ - val mii = new MII - val cfg = Flipped(new Mac_Config_Bundle) - - // val int_o = Output(Bool()) - - val isLoopBack = Output(Bool()) - val asyncReset = Input(AsyncReset()) -} - - -abstract class Mac(implicit p: Parameters) extends SwitchNode{ - - val io = IO(new MacIO) - - - val r_ClkDiv = Wire(UInt(8.W)) - val r_MiiNoPre = Wire(Bool()) - val r_CtrlData = Wire(UInt(16.W)) - val r_FIAD = Wire(UInt(5.W)) - val r_RGAD = Wire(UInt(5.W)) - val r_WCtrlData = Wire(Bool()) - val r_RStat = Wire(Bool()) - val r_ScanStat = Wire(Bool()) - val NValid_stat = Wire(Bool()) - val Busy_stat = Wire(Bool()) - val LinkFail = Wire(Bool()) - val Prsd = Wire(UInt(16.W)) - val WCtrlDataStart = Wire(Bool()) - val RStatStart = Wire(Bool()) - val UpdateMIIRX_DATAReg = Wire(Bool()) - - - - val TxStartFrm = Wire(Bool()) - val TxEndFrm = Wire(Bool()) - val TxUsedData = Wire(Bool()) - val TxData = Wire(UInt(8.W)) - val TxAbort = Wire(Bool()) - val TxDone = Wire(Bool()) - - - - - // Connecting Miim module - val miim = Module(new MIIM) - - miim.io.Divider := r_ClkDiv - miim.io.NoPre := r_MiiNoPre - miim.io.WCtrlData := r_WCtrlData - miim.io.CtrlData := r_CtrlData - miim.io.Fiad := r_FIAD - miim.io.Rgad := r_RGAD - miim.io.RStat := r_RStat - miim.io.ScanStat := r_ScanStat - - miim.io.mdi := io.mii.mdi - - Busy_stat := miim.io.Busy - LinkFail := miim.io.LinkFail - NValid_stat := miim.io.Nvalid - Prsd := miim.io.Prsd - WCtrlDataStart := miim.io.WCtrlDataStart - RStatStart := miim.io.RStatStart - UpdateMIIRX_DATAReg := miim.io.UpdateMIIRX_DATAReg - - io.mii.mdc := miim.io.mdc - io.mii.mdo := miim.io.mdo - io.mii.mdoEn := miim.io.mdoEn - - - - - - - - - - val r_LoopBck = Wire(Bool()) - val r_TxEn = Wire(Bool()) - val r_RxEn = Wire(Bool()) - val MRxDV_Lb = Wire(Bool()) - val MRxD_Lb = Wire(UInt(4.W)) - val Transmitting = Wire(Bool()) - val DribbleNibble = Wire(Bool()) - val LoadRxStatus = Wire(Bool()) - val r_HASH0 = Wire(UInt(32.W)) - val r_HASH1 = Wire(UInt(32.W)) - val r_IPGT = Wire(UInt(7.W)) - val r_IPGR1 = Wire(UInt(7.W)) - val r_IPGR2 = Wire(UInt(7.W)) - val r_CollValid = Wire(UInt(6.W)) - val r_ExDfrEn = Wire(Bool()) - val r_IFG = Wire(Bool()) - val TxB_IRQ = Wire(Bool()) - val TxE_IRQ = Wire(Bool()) - val RxB_IRQ = Wire(Bool()) - val RxE_IRQ = Wire(Bool()) - val Busy_IRQ = Wire(Bool()) - val r_FullD = Wire(Bool()) - val r_NoPre = Wire(Bool()) - val StartTxDone = Wire(Bool()) - val PerPacketCrcEn = Wire(Bool()) - val LateCollision = Wire(Bool()) - val DeferIndication = Wire(Bool()) - val LateCollLatched = Wire(Bool()) - val DeferLatched = Wire(Bool()) - val RstDeferLatched = Wire(Bool()) - val CarrierSenseLost = Wire(Bool()) - - - - io.cfg.WCtrlDataStart := WCtrlDataStart - io.cfg.RStatStart := RStatStart - io.cfg.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg - io.cfg.Prsd := Prsd - io.cfg.NValid_stat := NValid_stat - io.cfg.Busy_stat := Busy_stat - io.cfg.LinkFail := LinkFail - io.cfg.TxB_IRQ := TxB_IRQ - io.cfg.TxE_IRQ := TxE_IRQ - io.cfg.RxB_IRQ := RxB_IRQ - io.cfg.RxE_IRQ := RxE_IRQ - io.cfg.Busy_IRQ := Busy_IRQ - io.cfg.StartTxDone := StartTxDone - io.cfg.TxClk := io.mii.mtx_clk_pad_i - io.cfg.RxClk := io.mii.mrx_clk_pad_i - - r_FullD := io.cfg.r_FullD - r_ExDfrEn := io.cfg.r_ExDfrEn - r_LoopBck := io.cfg.r_LoopBck - r_IFG := io.cfg.r_IFG - r_NoPre := io.cfg.r_NoPre - r_TxEn := io.cfg.r_TxEn - r_RxEn := io.cfg.r_RxEn - r_HASH0 := io.cfg.r_HASH0 - r_HASH1 := io.cfg.r_HASH1 - r_IPGT := io.cfg.r_IPGT - r_IPGR1 := io.cfg.r_IPGR1 - r_IPGR2 := io.cfg.r_IPGR2 - r_CollValid := io.cfg.r_CollValid - r_MiiNoPre := io.cfg.r_MiiNoPre - r_ClkDiv := io.cfg.r_ClkDiv - r_WCtrlData := io.cfg.r_WCtrlData - r_RStat := io.cfg.r_RStat - r_ScanStat := io.cfg.r_ScanStat - r_RGAD := io.cfg.r_RGAD - r_FIAD := io.cfg.r_FIAD - r_CtrlData := io.cfg.r_CtrlData - - - - val RxData = Wire(UInt(8.W)) - val RxValid = Wire(Bool()) - val RxStartFrm = Wire(Bool()) - val RxEndFrm = Wire(Bool()) - val WillTransmit = Wire(Bool()) - val ResetCollision = Wire(Bool()) - val LatchedCrcError = Wire(Bool()) - val RxLateCollision = Wire(Bool()) - val StartTxAbort = Wire(Bool()) - val MaxCollisionOccured = Wire(Bool()) - val RetryLimit = Wire(Bool()) - val StatePreamble = Wire(Bool()) - val StateData = Wire(UInt(2.W)) - - - - - - - - - - - - - - - - - - - - - - - - - - val TxCarrierSense = Wire(Bool()) - val Collision = Wire(Bool()) - val CarrierSense_Tx2 = Wire(Bool()) - val RxEnSync = Wire(Bool()) - - - io.isLoopBack := r_LoopBck - - // Muxed MII receive data valid - MRxDV_Lb := Mux(r_LoopBck, io.mii.mtxen_pad_o, io.mii.mrxdv_pad_i & RxEnSync) - - // Muxed MII Receive Data - MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i) - - - val txethmac = withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx)) - - txethmac.io.TxStartFrm := TxStartFrm - txethmac.io.TxEndFrm := TxEndFrm - txethmac.io.TxData := TxData - txethmac.io.CarrierSense := TxCarrierSense - txethmac.io.Collision := Collision - txethmac.io.CrcEn := PerPacketCrcEn - txethmac.io.FullD := r_FullD - txethmac.io.IPGT := r_IPGT - txethmac.io.IPGR1 := r_IPGR1 - txethmac.io.IPGR2 := r_IPGR2 - txethmac.io.CollValid := r_CollValid - txethmac.io.ExDfrEn := r_ExDfrEn - - io.mii.mtxd_pad_o := txethmac.io.MTxD - io.mii.mtxen_pad_o := txethmac.io.MTxEn - TxDone := txethmac.io.TxDone - TxAbort := txethmac.io.TxAbort - TxUsedData := txethmac.io.TxUsedData - WillTransmit := txethmac.io.WillTransmit - ResetCollision := txethmac.io.ResetCollision - StartTxDone := txethmac.io.StartTxDone - StartTxAbort := txethmac.io.StartTxAbort - MaxCollisionOccured := txethmac.io.MaxCollisionOccured - LateCollision := txethmac.io.LateCollision - DeferIndication := txethmac.io.DeferIndication - StatePreamble := txethmac.io.StatePreamble - StateData := txethmac.io.StateData - - - - - - val RxByteCnt = Wire(UInt(16.W)) - val RxByteCntEq0 = Wire(Bool()) - val RxByteCntGreat2 = Wire(Bool()) - val RxCrcError = Wire(Bool()) - val RxStateIdle = Wire(Bool()) - val RxStatePreamble = Wire(Bool()) - val RxStateSFD = Wire(Bool()) - val RxStateData = Wire(UInt(2.W)) - - - - val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx)) - - rxethmac.io.MRxDV := MRxDV_Lb - rxethmac.io.MRxD := MRxD_Lb - rxethmac.io.Transmitting := Transmitting - rxethmac.io.r_IFG := r_IFG - rxethmac.io.r_HASH0 := r_HASH0 - rxethmac.io.r_HASH1 := r_HASH1 - - RxData := rxethmac.io.RxData - RxValid := rxethmac.io.RxValid - RxStartFrm := rxethmac.io.RxStartFrm - RxEndFrm := rxethmac.io.RxEndFrm - RxByteCnt := rxethmac.io.ByteCnt - RxByteCntEq0 := rxethmac.io.ByteCntEq0 - RxByteCntGreat2 := rxethmac.io.ByteCntGreat2 - RxCrcError := rxethmac.io.CrcError - RxStateIdle := rxethmac.io.StateIdle - RxStatePreamble := rxethmac.io.StatePreamble - RxStateSFD := rxethmac.io.StateSFD - RxStateData := rxethmac.io.StateData - - - - withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) { - // MII Carrier Sense Synchronization - CarrierSense_Tx2 := ShiftRegister(io.mii.mcrs_pad_i, 2, false.B, true.B) - - TxCarrierSense := ~r_FullD & CarrierSense_Tx2 - - val Collision_Tx1 = RegNext(io.mii.mcoll_pad_i, false.B) - val Collision_Tx2 = RegInit(false.B) - - when(ResetCollision){ - Collision_Tx2 := false.B - } .elsewhen(Collision_Tx1){ - Collision_Tx2 := true.B - } - - - // Synchronized Collision - Collision := ~r_FullD & Collision_Tx2 - - } - - - - - withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) { - val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B) - - Transmitting := ~r_FullD & WillTransmit_q - RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mii.mrxdv_pad_i) - } - - - - - - - - - - - val macstatus = Module(new MacStatus) - - macstatus.io.asyncReset := io.asyncReset - macstatus.io.MRxClk := io.mii.mrx_clk_pad_i - macstatus.io.RxCrcError := RxCrcError - macstatus.io.MRxDV := MRxDV_Lb - macstatus.io.RxStateSFD := RxStateSFD - macstatus.io.RxStateData := RxStateData - macstatus.io.RxStatePreamble := RxStatePreamble - macstatus.io.RxStateIdle := RxStateIdle - macstatus.io.Transmitting := Transmitting - macstatus.io.RxByteCnt := RxByteCnt - macstatus.io.RxByteCntEq0 := RxByteCntEq0 - macstatus.io.RxByteCntGreat2 := RxByteCntGreat2 - macstatus.io.MRxD := MRxD_Lb - macstatus.io.Collision := io.mii.mcoll_pad_i - macstatus.io.CollValid := r_CollValid - macstatus.io.StartTxDone := StartTxDone - macstatus.io.StartTxAbort := StartTxAbort - macstatus.io.MTxClk := io.mii.mtx_clk_pad_i - macstatus.io.MaxCollisionOccured := MaxCollisionOccured - macstatus.io.LateCollision := LateCollision - macstatus.io.DeferIndication := DeferIndication - macstatus.io.TxStartFrm := TxStartFrm - macstatus.io.StatePreamble := StatePreamble - macstatus.io.StateData := StateData - macstatus.io.CarrierSense := CarrierSense_Tx2 - macstatus.io.Loopback := r_LoopBck - macstatus.io.r_FullD := r_FullD - macstatus.io.RstDeferLatched := RstDeferLatched - - LatchedCrcError := macstatus.io.LatchedCrcError - RxLateCollision := macstatus.io.RxLateCollision - DribbleNibble := macstatus.io.DribbleNibble - LoadRxStatus := macstatus.io.LoadRxStatus - RetryLimit := macstatus.io.RetryLimit - LateCollLatched := macstatus.io.LateCollLatched - DeferLatched := macstatus.io.DeferLatched - CarrierSenseLost := macstatus.io.CarrierSenseLost - - - - - - - - - - - - - - - - - - - - - val macTileLinkTx = Module(new MacTileLinkTx) - - RstDeferLatched := macTileLinkTx.io.RstDeferLatched - TxStartFrm := macTileLinkTx.io.TxStartFrm - TxEndFrm := macTileLinkTx.io.TxEndFrm - TxData := macTileLinkTx.io.TxData - macTileLinkTx.io.TxUsedData := TxUsedData - macTileLinkTx.io.TxAbort := TxAbort - macTileLinkTx.io.TxDone := TxDone - - macTileLinkTx.io.RetryLimit := RetryLimit - macTileLinkTx.io.LateCollLatched := LateCollLatched - macTileLinkTx.io.DeferLatched := DeferLatched - macTileLinkTx.io.CarrierSenseLost := CarrierSenseLost - PerPacketCrcEn := macTileLinkTx.io.PerPacketCrcEn - - macTileLinkTx.io.r_TxEn := r_TxEn - - macTileLinkTx.io.isTxIdle := txethmac.io.isTxIdle - - macTileLinkTx.io.MTxClk := io.mii.mtx_clk_pad_i - macTileLinkTx.io.asyncReset := io.asyncReset - - - - - - - - - - - - - val macTileLinkRx = Module(new MacTileLinkRx) - macTileLinkRx.io.DribbleNibble := DribbleNibble - macTileLinkRx.io.LatchedCrcError := LatchedCrcError - macTileLinkRx.io.RxLateCollision := RxLateCollision - macTileLinkRx.io.LoadRxStatus := LoadRxStatus - - macTileLinkRx.io.RxData := RxData - macTileLinkRx.io.RxValid := RxValid - macTileLinkRx.io.RxStartFrm := RxStartFrm - macTileLinkRx.io.RxEndFrm := RxEndFrm - - Busy_IRQ := macTileLinkRx.io.Busy_IRQ - - macTileLinkRx.io.r_RxEn := r_RxEn - - - - macTileLinkRx.io.MRxClk := io.mii.mrx_clk_pad_i - macTileLinkRx.io.asyncReset := io.asyncReset - - TxB_IRQ := false.B - TxE_IRQ := false.B - RxB_IRQ := false.B - RxE_IRQ := false.B - -} - - - - - diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala deleted file mode 100644 index 32df354..0000000 --- a/src/main/scala/Switch/MacRegisters.scala +++ /dev/null @@ -1,349 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - -import freechips.rocketchip.regmapper._ -import freechips.rocketchip.tilelink._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.interrupts._ - -class Mac_Config_Bundle extends Bundle{ - val WCtrlDataStart = Input(Bool()) - val RStatStart = Input(Bool()) - val UpdateMIIRX_DATAReg = Input(Bool()) - val Prsd = Input(UInt(16.W)) - val NValid_stat = Input(Bool()) - val Busy_stat = Input(Bool()) - val LinkFail = Input(Bool()) - val TxB_IRQ = Input(Bool()) - val TxE_IRQ = Input(Bool()) - val RxB_IRQ = Input(Bool()) - val RxE_IRQ = Input(Bool()) - val Busy_IRQ = Input(Bool()) - val StartTxDone = Input(Bool()) - val TxClk = Input(Bool()) - val RxClk = Input(Bool()) - - val r_FullD = Output(Bool()) - val r_ExDfrEn = Output(Bool()) - val r_LoopBck = Output(Bool()) - val r_IFG = Output(Bool()) - val r_NoPre = Output(Bool()) - val r_TxEn = Output(Bool()) - val r_RxEn = Output(Bool()) - val r_HASH0 = Output(UInt(32.W)) - val r_HASH1 = Output(UInt(32.W)) - val r_IPGT = Output(UInt(7.W)) - val r_IPGR1 = Output(UInt(7.W)) - val r_IPGR2 = Output(UInt(7.W)) - val r_CollValid = Output(UInt(6.W)) - val r_MiiNoPre = Output(Bool()) - val r_ClkDiv = Output(UInt(8.W)) - val r_WCtrlData = Output(Bool()) - val r_RStat = Output(Bool()) - val r_ScanStat = Output(Bool()) - val r_RGAD = Output(UInt(5.W)) - val r_FIAD = Output(UInt(5.W)) - val r_CtrlData = Output(UInt(16.W)) - - -} - - -class MacRegIO extends Mac_Config_Bundle{ - val asyncReset = Input(AsyncReset()) - -} - - - -class MacReg(chn: Int)(implicit p: Parameters) extends LazyModule{ - - - - - - // DTS - val dtsdevice = new SimpleDevice(s"mac$chn",Seq(s"mac_$chn")) - val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int)) - - - val configNode = TLRegisterNode( - address = Seq(AddressSet(0x30000000L + 0x100*chn, 0x000000ffL)), - device = dtsdevice, - concurrency = 1, - beatBytes = 32/8, - executable = true - ) - lazy val module = new MacRegImp(this) -} - -class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{ - - val io: MacRegIO = IO(new MacRegIO) - val (int, _) = outer.int_node.out(0) - - - - val FullD = RegInit(false.B) - val ExDfrEn = RegInit(false.B) - val LoopBck = RegInit(false.B) - val IFG = RegInit(false.B) - val NoPre = RegInit(false.B) - val TxEn = RegInit(false.B) - val RxEn = RegInit(false.B) - - // Interrupt generation - val irq_txb = RegInit(false.B) - val irq_txe = RegInit(false.B) - val irq_rxb = RegInit(false.B) - val irq_rxe = RegInit(false.B) - val irq_busy = RegInit(false.B) - - - - - val INT_MASK = RegInit(0.U(7.W)) // INT_MASK Register - val IPGT = RegInit("h12".U(7.W)) // IPGT Register - val IPGR1 = RegInit("h0C".U(7.W)) // IPGR1 Register - val IPGR2 = RegInit("h12".U(7.W)) - - val collValid = RegInit("h3f".U(6.W)) - - val clkDiv = RegInit("h64".U(8.W)) - val miiNoPre = RegInit(false.B) - - - val scanStat = RegInit(false.B) - val readStat = RegInit(false.B) - val wCtrlData = RegInit(false.B) - - when(io.RStatStart){ readStat := false.B } - when(io.WCtrlDataStart){ wCtrlData := false.B } - - val FIAD = RegInit(0.U(5.W)) - val RGAD = RegInit(0.U(5.W)) - - val MIITX_DATA = RegInit(0.U(16.W)) // MIITX_DATA Register - - val MIIRX_DATA = RegEnable(io.Prsd, 0.U(16.W), io.UpdateMIIRX_DATAReg) // MIIRX_DATA Register - - - - val HASH0 = RegInit(0.U(32.W)) - val HASH1 = RegInit(0.U(32.W)) - - - - - - - outer.configNode.regmap( - ( 0 << 2 ) -> - RegFieldGroup("MODER", Some("Mode Register"), Seq( - RegField(1, RxEn , RegFieldDesc( "RxEn", "RxEn", reset = Some(0))) , - RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ), - RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ), - RegField.r(1, 0.U , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ), - RegField.r(1, 0.U , RegFieldDesc( "Iam", "Iam Unused", reset = Some(0) ) ), - RegField.r(1, 0.U , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ), - RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ), - RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ), - RegField.r(1, 0.U, RegFieldDesc( "NoBckof", "NoBckof", reset = Some(0) ) ), - RegField(1, ExDfrEn, RegFieldDesc( "ExDfrEn", "ExDfrEn", reset = Some(0) ) ), - RegField(1, FullD , RegFieldDesc( "FullD", "FullD", reset = Some(0) ) ), - RegField.r(1, 0.U), - RegField.r(1, 0.U, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ), - RegField.r(1, 0.U, RegFieldDesc( "CrcEn", "CrcEn", reset=Some(1)) ), - RegField.r(1, 1.U , RegFieldDesc( "HugEn", "HugEn", reset=Some(0)) ), - RegField.r(1, 1.U , RegFieldDesc( "Pad", "Pad", reset=Some(1)) ), - RegField.r(1, 1.U, RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) ) - )), - - ( 1 << 2 ) -> - RegFieldGroup("INT_SOURCE", Some("Interrupt Source Register"), Seq( - RegField(1, irq_txb, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txb := 0.U }; true.B }), RegFieldDesc("txb", "txb", reset=Some(0))), - RegField(1, irq_txe, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txe := 0.U }; true.B }), RegFieldDesc("txe", "txe", reset=Some(0))), - RegField(1, irq_rxb, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxb := 0.U }; true.B }), RegFieldDesc("rxb", "rxb", reset=Some(0))), - RegField(1, irq_rxe, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxe := 0.U }; true.B }), RegFieldDesc("rxe", "rxe", reset=Some(0))), - RegField(1, irq_busy, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_busy := 0.U }; true.B }), RegFieldDesc("busy", "busy", reset=Some(0))), - RegField.r(1, 0.U, RegFieldDesc("txc", "txc", reset=Some(0))), - RegField.r(1, 0.U, RegFieldDesc("rxc", "rxc", reset=Some(0))), - )), - - ( 2 << 2 ) -> - RegFieldGroup("INT_MASK", Some("Interrupt Mask Register"), Seq( - RegField(7, INT_MASK) - )), - - ( 3 << 2 ) -> - RegFieldGroup("IPGT", Some("Back to Back Inter Packet Gap Register"), Seq( - RegField(7, IPGT, RegFieldDesc("IPGT", "IPGT", reset=Some(0x12))) - )), - - ( 4 << 2 ) -> - RegFieldGroup("IPGR1", Some("Non Back to Back Inter Packet Gap Register 1"), Seq( - RegField(7, IPGR1, RegFieldDesc("IPGR1", "IPGR1", reset=Some(0xc))) - )), - - ( 5 << 2 ) -> - RegFieldGroup("IPGR2", Some("Non Back to Back Inter Packet Gap Register 2"), Seq( - RegField(7, IPGR2, RegFieldDesc("IPGR2", "IPGR2", reset=Some(0x12))) - )), - - ( 7 << 2 ) -> - RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq( - RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))), - RegField.r(10,0.U), - RegField.r(4, 0.U, RegFieldDesc("maxRet", "Maximum Retry", reset=Some(0xf))), - )), - - - ( 10 << 2 ) -> - RegFieldGroup("MIIMODER", Some("MII Mode Register"), Seq( - RegField(8, clkDiv, RegFieldDesc("clkDiv", "Clock Divider", reset=Some(0x64))), - RegField(1, miiNoPre, RegFieldDesc("MIINoPre", "NO Preamble", reset=Some(0x0))), - )), - - ( 11 << 2 ) -> - RegFieldGroup("MIICOMMAND", Some("MII Command Register"), Seq( - RegField(1, scanStat, RegFieldDesc("scanStat", "Scan Status", reset=Some(0x0))), - RegField(1, readStat, RegFieldDesc("readStat", "Read Status", reset=Some(0x0))), - RegField(1, wCtrlData, RegFieldDesc("wCtrlData", "Write Control Data", reset=Some(0x0))), - )), - - ( 12 << 2 ) -> - RegFieldGroup("MIIADDRESS", Some("MII Address Register"), Seq( - RegField(5, FIAD, RegFieldDesc("FIAD", "PHY Address", reset=Some(0x0))), - RegField.r(3 ,0.U), - RegField(5, RGAD, RegFieldDesc("RGAD", "Register Address", reset=Some(0x0))), - )), - - ( 13 << 2 ) -> - RegFieldGroup("MIITX_DATA", Some("MII Transmit Data"), - RegField.bytes(MIITX_DATA) - ), - - ( 14 << 2 ) -> - RegFieldGroup("MIIRX_DATA", Some("MII Receive Data"), Seq( - RegField.r(16, MIIRX_DATA) - )), - - ( 15 << 2 ) -> - RegFieldGroup("MIISTATUS", Some("MII Status Register"), Seq( - RegField.r(1, io.LinkFail), - RegField.r(1, io.Busy_stat), - RegField.r(1, io.NValid_stat), - )), - - ( 16 << 2 ) -> - RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( - RegField(32) - )), - - ( 17 << 2 ) -> - RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( - RegField(32) - )), - - ( 18 << 2 ) -> - RegFieldGroup("HASH0", Some("HASH Register 0"), - RegField.bytes(HASH0) - ), - - ( 19 << 2 ) -> - RegFieldGroup("HASH1", Some("HASH Register 1"), - RegField.bytes(HASH1) - ), - - ) - - - - - io.r_FullD := FullD - io.r_ExDfrEn := ExDfrEn - io.r_LoopBck := LoopBck - io.r_IFG := IFG - io.r_NoPre := NoPre - io.r_TxEn := TxEn - io.r_RxEn := RxEn - - io.r_IPGT := IPGT - io.r_IPGR1 := IPGR1 - io.r_IPGR2 := IPGR2 - io.r_CollValid := collValid - io.r_MiiNoPre := miiNoPre - io.r_ClkDiv := clkDiv - io.r_WCtrlData := wCtrlData - io.r_RStat := readStat - io.r_ScanStat := scanStat - io.r_RGAD := RGAD - io.r_FIAD := FIAD - io.r_CtrlData := MIITX_DATA - - io.r_HASH1 := HASH1 - io.r_HASH0 := HASH0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - when(io.TxB_IRQ){ irq_txb := true.B } - when(io.TxE_IRQ){ irq_txe := true.B } - when(io.RxB_IRQ){ irq_rxb := true.B } - when(io.RxE_IRQ){ irq_rxe := true.B } - when(io.Busy_IRQ){ irq_busy := true.B } - - - - - - - - - // Generating interrupt signal - // io.int_o := - int(0) := - (irq_txb & INT_MASK.extract(0) ) | - (irq_txe & INT_MASK.extract(1) ) | - (irq_rxb & INT_MASK.extract(2) ) | - (irq_rxe & INT_MASK.extract(3) ) | - (irq_busy & INT_MASK.extract(4) ) - - - - -} - - diff --git a/src/main/scala/Switch/Parameters.scala b/src/main/scala/Switch/Parameters.scala deleted file mode 100644 index a2b5ebd..0000000 --- a/src/main/scala/Switch/Parameters.scala +++ /dev/null @@ -1,41 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.stage._ -import freechips.rocketchip.diplomacy._ - -import org.chipsalliance.cde.config._ - -abstract class SwitchModule(implicit val p: Parameters) extends Module with HasSwitchParameters { def io: Record } -abstract class SwitchBundle(implicit val p: Parameters) extends Bundle with HasSwitchParameters - - -case object SwitchParamsKey extends Field[SwitchSetting] - - -case class SwitchSetting( - // isTileLink: Boolean = true - chn: Int = 3 -){ - require( chn > 0 , "Error, at least one mac chn!\n" ) - require( chn <= 16, "Error, register address between only 0x000~0x1000, 0x100 for each!\n" ) -} - -trait HasSwitchParameters { - implicit val p: Parameters - - val switchSetting = p(SwitchParamsKey) - - def chn = switchSetting.chn - -} - -class SwitchCfg extends Config((_, _, _) => { - case SwitchParamsKey => SwitchSetting() -}) - -class EfConfig extends Config((site, here, up) => { - case SwitchParamsKey => SwitchSetting( - chn = 2, - ) -}) \ No newline at end of file diff --git a/src/main/scala/Switch/PiPoBuff.scala b/src/main/scala/Switch/PiPoBuff.scala deleted file mode 100644 index 037d61d..0000000 --- a/src/main/scala/Switch/PiPoBuff.scala +++ /dev/null @@ -1,175 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - -import MAC._ - - - - - - - - - -class PiPoBuffBase[T<:Data]( dp: Int, val threshold: Int = 32) extends Module{ - - class PiPoBuffIO extends Bundle{ - val enq = Flipped(Decoupled(new Mac_Stream_Bundle)) - val deq = Decoupled(new Mac_Stream_Bundle) - } - - val io: PiPoBuffIO = IO(new PiPoBuffIO) - - val isEnqPi = RegInit(true.B) - val isEnqPo = ~isEnqPi - - val isDeqPi = RegInit(true.B) - val isDeqPo = ~isDeqPi - - - val buff = for( i <- 0 until 2 ) yield { Module(new Queue( new Mac_Stream_Bundle, dp )) } - val isReach = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val cnt = RegInit(0.U((log2Ceil(dp)).W)) - - - - buff(0).io.enq.valid := isEnqPi & io.enq.valid - buff(0).io.enq.bits := io.enq.bits - - buff(1).io.enq.valid := isEnqPo & io.enq.valid - buff(1).io.enq.bits := io.enq.bits - - io.enq.ready := - Mux1H(Seq( - isEnqPi -> buff(0).io.enq.ready, - isEnqPo -> buff(1).io.enq.ready - )) - - when( io.enq.fire & io.enq.bits.isLast ){ - isEnqPi := ~isEnqPi - } - - - - when( io.enq.fire ){ - when( io.enq.bits.isLast ){ - cnt := 0.U - } .elsewhen( io.enq.bits.isStart ){ - cnt := 1.U - } .otherwise{ - cnt := cnt + 1.U - } - } - - - - when( io.enq.fire ){ - when( io.enq.bits.isStart ){ - when( isEnqPi ){ isReach(0) := false.B } - when( isEnqPo ){ isReach(1) := false.B } - } .elsewhen( - io.enq.bits.isLast || - (if( threshold != 0 ) { cnt === threshold.U } else {false.B}) - ){ - when( isEnqPi ){ isReach(0) := true.B } - when( isEnqPo ){ isReach(1) := true.B } - } - } - - - when( io.deq.fire & io.deq.bits.isLast ){ - isDeqPi := ~isDeqPi - } - - io.deq.valid := - Mux1H(Seq( - isDeqPi -> ( buff(0).io.deq.valid & isReach(0) ), - isDeqPo -> ( buff(1).io.deq.valid & isReach(1) ), - )) - - io.deq.bits := - Mux1H(Seq( - isDeqPi -> buff(0).io.deq.bits, - isDeqPo -> buff(1).io.deq.bits, - )) - - buff(0).io.deq.ready := io.deq.ready & isReach(0) & isDeqPi - buff(1).io.deq.ready := io.deq.ready & isReach(1) & isDeqPo -} - - - -class TxBuff(threshold: Int = 8) extends PiPoBuffBase(2048, threshold) - - - - -class Rx_MuxInfo_Bundle extends Bundle{ - val dest = Valid(UInt((48+1).W)) - val source = Valid(UInt((48+1).W)) - - def isBroadcast = dest.bits.extract(40) -} - -class RxBuff(threshold: Int = 8) extends PiPoBuffBase(2048, threshold){ - val mInfo = IO(new Rx_MuxInfo_Bundle) - - val destReg = for( i <- 0 until 2 ) yield { Reg(Vec(6, UInt(8.W))) } - val destValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } - - val sourceReg = for( i <- 0 until 2 ) yield { Reg(Vec(6, UInt(8.W))) } - val sourceValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } - - when( io.enq.fire ){ - when( cnt < 6.U ){ - when( isEnqPi ){ destReg(0)(cnt) := io.enq.bits.data } - when( isEnqPo ){ destReg(1)(cnt) := io.enq.bits.data } - } .elsewhen( cnt < 12.U ){ - when( isEnqPi ){ sourceReg(0)(cnt-6.U) := io.enq.bits.data } - when( isEnqPo ){ sourceReg(1)(cnt-6.U) := io.enq.bits.data } - } - } - - - when( io.deq.fire & io.deq.bits.isLast ){ - when( isDeqPi ) { destValid(0) := false.B; sourceValid(0) := false.B } - when( isDeqPo ) { destValid(1) := false.B; sourceValid(1) := false.B } - } .elsewhen( io.enq.fire & cnt === 5.U ){ - when( isEnqPi ) { destValid(0) := true.B } - when( isEnqPo ) { destValid(1) := true.B } - } .elsewhen( io.enq.fire & cnt === 11.U ){ - when( isEnqPi ) { sourceValid(0) := true.B } - when( isEnqPo ) { sourceValid(1) := true.B } - } - - mInfo.dest.valid := - Mux1H(Seq( - isDeqPi -> destValid(0), - isDeqPo -> destValid(1), - )) - - mInfo.dest.bits := - Mux1H(Seq( - isDeqPi -> Cat(destReg(0)), - isDeqPo -> Cat(destReg(1)), - )) - - mInfo.source.valid := - Mux1H(Seq( - isDeqPi -> sourceValid(0), - isDeqPo -> sourceValid(1), - )) - - mInfo.source.bits := - Mux1H(Seq( - isDeqPi -> Cat(sourceReg(0)), - isDeqPo -> Cat(sourceReg(1)), - )) - - -} - - - diff --git a/src/main/scala/Switch/Robin.scala b/src/main/scala/Switch/Robin.scala deleted file mode 100644 index 3c7723b..0000000 --- a/src/main/scala/Switch/Robin.scala +++ /dev/null @@ -1,70 +0,0 @@ - -package Switch - -import chisel3._ -import chisel3.util._ -import chisel3.util.random._ - - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -import MAC._ - -class Robin_Bundle(implicit p: Parameters) extends SwitchBundle{ - val rx = Decoupled(new Mac_Stream_Bundle) - val mInfo = new Rx_MuxInfo_Bundle - -} - -class Robin(implicit p: Parameters) extends SwitchModule{ - class RobinIO extends Bundle{ - val enq = Vec( chn+1, Flipped(new Robin_Bundle) ) - val deq = new Robin_Bundle - val sel = Output(UInt( (log2Ceil(chn+1)).W )) - } - - val io: RobinIO = IO(new RobinIO) - - - - - val isLock = RegInit(false.B) - val lockChn = Reg(UInt((log2Ceil(chn+1)).W)) - io.sel := lockChn - - val lfsr = ~LFSR( (log2Ceil(chn+1)+1), ~isLock) - - for( i <- 0 until chn+1 ) { - when( i.U === lfsr ){ - when( io.enq(i).mInfo.dest.valid ){ - assert( ~isLock ) - isLock := true.B - lockChn := lfsr - } - } - } - - when( io.deq.rx.fire & io.deq.rx.bits.isLast ){ - assert( isLock ) - isLock := false.B - } - - - for( i <- 0 until chn+1 ) { - io.enq(i).rx.ready := false.B - } - when( ~isLock ){ - io.deq.rx.valid := false.B - io.deq.rx.bits := 0.U.asTypeOf(new Mac_Stream_Bundle) - io.deq.mInfo.dest.valid := false.B - io.deq.mInfo.dest.bits := 0.U - io.deq.mInfo.source.valid := false.B - io.deq.mInfo.source.bits := 0.U - } .otherwise{ - io.deq <> io.enq(lockChn) - } - - -} \ No newline at end of file diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala deleted file mode 100644 index 7bf96bb..0000000 --- a/src/main/scala/Switch/Switch.scala +++ /dev/null @@ -1,174 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - -import MAC._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ - -import chisel3.experimental.dataview._ - - -class SwitchIO(implicit p: Parameters) extends SwitchBundle{ - val mii = Vec( chn, new MII ) - - val isLoopBack = Output(Vec( chn, Bool())) - val asyncReset = Input(AsyncReset()) -} - - -class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters{ - - val tlClientNode = TLClientNode(Seq(TLMasterPortParameters.v1( - Seq(TLMasterParameters.v1( - name = "DMA", - sourceId = IdRange(0, chn), - )) - ))) - - - - - val macReg = for( i <- 0 until chn ) yield { LazyModule(new MacReg(i)) } - val dmaReg = LazyModule(new DmaReg) - - lazy val module = new SwitchImp(this) - -} - -class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{ - val io = IO(new SwitchIO) - val ( dma_bus, dma_edge ) = outer.tlClientNode.out.head - - val mac = ( 0 until chn ).map{ i => - Module(new MacNode) - } - - ( 0 until chn ).map{ i => - mac(i).io.mii <> io.mii(i) - mac(i).io.asyncReset := io.asyncReset - io.isLoopBack(i) := mac(i).io.isLoopBack - - outer.macReg(i).module.io.asyncReset := io.asyncReset - outer.macReg(i).module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(i).io.cfg - } - - - val dmaMst = Module(new DmaNode(dma_edge)) - - dmaMst.io.cfg <> outer.dmaReg.module.io.cfg - - - dmaMst.io.dmaMst.D.bits := dma_bus.d.bits - dmaMst.io.dmaMst.D.valid := dma_bus.d.valid - dma_bus.d.ready := dmaMst.io.dmaMst.D.ready - dma_bus.a.valid := dmaMst.io.dmaMst.A.valid - dma_bus.a.bits := dmaMst.io.dmaMst.A.bits - dmaMst.io.dmaMst.A.ready := dma_bus.a.ready - - - - - val robin = Module(new Robin) - - // dmaMst.ex.tx <> - // <> mac(0).ex.tx - - for( i <- 0 until chn ){ - mac(i).ex.rx <> robin.io.enq(i).rx - mac(i).ex.mInfo <> robin.io.enq(i).mInfo - } - - dmaMst.ex.rx <> robin.io.enq(chn+1-1).rx - dmaMst.ex.mInfo <> robin.io.enq(chn+1-1).mInfo - - - val destTable = Wire( Vec( chn+1, Vec( 4, UInt(48.W) ) ) ) - for( i <- 0 until chn+1 ){ - destTable(i)(0) := "h102030405A00".U + i.U - destTable(i)(1) := "h102030405B00".U + i.U - destTable(i)(2) := "h102030405C00".U + i.U - destTable(i)(3) := "h102030405D00".U + i.U - } - - - - val isHit = Reg(Bool()) - val destChn = Reg(UInt((log2Ceil(chn+1)).W)) - val isMuxBusy = RegInit(false.B) - val dmaSelIn = Reg(UInt((log2Ceil(chn)).W)); dmaMst.io.selIn := dmaSelIn - - - when( robin.io.deq.rx.fire & robin.io.deq.rx.bits.isLast ){ - assert( isMuxBusy ) - isMuxBusy := false.B - } .elsewhen( robin.io.deq.mInfo.dest.valid & ~isMuxBusy ){ - - isMuxBusy := true.B - isHit := false.B - dmaSelIn := robin.io.sel - - when( robin.io.sel === (chn+1-1).U ){ //DMA - isHit := true.B - destChn := dmaMst.io.selOut - } .otherwise{ - for( i <- 0 until chn+1 ){ - when( - robin.io.deq.mInfo.dest.bits === destTable(i)(0) || - robin.io.deq.mInfo.dest.bits === destTable(i)(1) || - robin.io.deq.mInfo.dest.bits === destTable(i)(2) || - robin.io.deq.mInfo.dest.bits === destTable(i)(3) - ){ - isHit := true.B - destChn := i.U - } - } - } - - - - - } - - val tempTxPort = Wire( Vec( chn+1, Decoupled(new Mac_Stream_Bundle) ) ) - for( i <- 0 until chn ){ - mac(i).ex.tx.valid := tempTxPort(i).valid - mac(i).ex.tx.bits := tempTxPort(i).bits - tempTxPort(i).ready := mac(i).ex.tx.ready - } - dmaMst.ex.tx.valid := tempTxPort(chn+1-1).valid - dmaMst.ex.tx.bits := tempTxPort(chn+1-1).bits - tempTxPort(chn+1-1).ready := dmaMst.ex.tx.ready - - - val allTxReady = tempTxPort.map{ x => x.ready }.foldLeft(true.B)(_&_) - - - for( i <- 0 until chn+1 ){ - tempTxPort(i).valid := false.B - tempTxPort(i).bits := 0.U.asTypeOf(new Mac_Stream_Bundle) - } - robin.io.deq.rx.ready := false.B - - when( isMuxBusy ){ - when( isHit ){ - tempTxPort(destChn).valid := robin.io.deq.rx.valid - tempTxPort(destChn).bits := robin.io.deq.rx.bits - robin.io.deq.rx.ready := tempTxPort(destChn).ready - } .otherwise{ - for( i <- 0 until chn+1 ){ - when( i.U =/= robin.io.sel ){ - tempTxPort(i).valid := robin.io.deq.rx.valid & allTxReady - tempTxPort(i).bits := robin.io.deq.rx.bits - } - } - robin.io.deq.rx.ready := allTxReady - } - } - -} - diff --git a/src/main/scala/Switch/SwitchMux.scala.bk b/src/main/scala/Switch/SwitchMux.scala.bk deleted file mode 100644 index f4aea60..0000000 --- a/src/main/scala/Switch/SwitchMux.scala.bk +++ /dev/null @@ -1,159 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - - - - -abstract class SwitchMuxBase(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{ - - class MacTileLinkMasterIO extends Bundle{ - val A = Decoupled(new TLBundleA(edgeOut.bundle)) - val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle))) - } - - class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{ - val dmaMst = new MacTileLinkMasterIO - - val triTx = Input(Bool()) - val triRx = Output(Bool()) - val r_TxPtr = Input(UInt(32.W)) - val r_RxPtr = Input(UInt(32.W)) - val r_TxLen = Input(UInt(16.W)) - val r_RxLen = Output(UInt(16.W)) - - val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle)) - val txDeq = Vec(chn, new Transmit_Bundle) - - } - - val io: SwitchMuxIO = IO(new SwitchMuxIO) - val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D) - - val rxBuff = Module(new RxBuff) - rxBuff.io.enq <> io.rxEnq(0) - - - val txBuff = Module(new TxBuff) - txBuff.io.deq <> io.txDeq(0) - - def stateIdle = 0.U - def stateRx = 1.U - def stateTx = 2.U - - val stateNxt = Wire(UInt(2.W)) - val stateCur = RegNext(stateNxt, stateIdle) - val stateDMA = RegInit(0.U(2.W)) - - when( stateNxt =/= stateIdle && stateCur === stateIdle ){ - stateDMA := 1.U - } .elsewhen( io.dmaMst.A.fire ){ - stateDMA := 2.U - } .elsewhen( io.dmaMst.D.fire & isLastD ){ - when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){ - stateDMA := 0.U - } .elsewhen( stateCur === stateRx & rxBuff.io.deq.data.valid ){ - stateDMA := 0.U - } .otherwise{ - stateDMA := 1.U - } - } - - - - stateNxt := - Mux1H(Seq( - ( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ), - ( stateCur === stateRx ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ), - ( stateCur === stateTx ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ), - )) - - io.triRx := rxBuff.io.deq.ctrl.fire - io.r_RxLen := RegEnable( rxBuff.io.deq.ctrl.bits.LatchedRxLength, rxBuff.io.deq.ctrl.fire ) - rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD - - - txBuff.io.enq.resp.ready := true.B - - - - - - val dmaAValid = RegInit(false.B) - val dmaABits = Reg(new TLBundleA(edgeOut.bundle)) - - - val dmaAddress = Reg( UInt(32.W) ) - - when( stateCur === stateIdle & stateNxt === stateTx ){ - dmaAddress := io.r_TxPtr - } .elsewhen( stateCur === stateIdle & stateNxt === stateRx ){ - dmaAddress := io.r_RxPtr - } .elsewhen( io.dmaMst.A.fire ){ - dmaAddress := dmaAddress + 1.U - } - - rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx) - assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) ) - - rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle - - when( io.dmaMst.A.fire ){ - dmaAValid := false.B - }.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){ - dmaAValid := true.B - dmaABits := - edgeOut.Get( - fromSource = 0.U, - toAddress = dmaAddress, - lgSize = log2Ceil(8/8).U, - )._2 - } .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) { - dmaAValid := true.B - dmaABits := - edgeOut.Put( - fromSource = 0.U, - toAddress = dmaAddress, - lgSize = log2Ceil(8/8).U, - data = rxBuff.io.deq.data.bits, - mask = "b1".U, - )._2 - } - - - io.dmaMst.A.valid := dmaAValid - io.dmaMst.A.bits := dmaABits - - - - txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx - txBuff.io.enq.req.bits.data := io.dmaMst.D.bits.data - txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr - txBuff.io.enq.req.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen) - - - io.dmaMst.D.ready := - Mux1H(Seq( - ( stateCur === stateRx ) -> true.B, - ( stateCur === stateTx ) -> txBuff.io.enq.req.ready, - )) - - - -} - - - - -trait SwitchMuxDMATx{ this: SwitchMuxBase => - -} - -class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchMuxBase(TLEdgeOut) -with SwitchMuxDMATx diff --git a/src/main/scala/Switch/SwitchNode.scala b/src/main/scala/Switch/SwitchNode.scala deleted file mode 100644 index 4f66de4..0000000 --- a/src/main/scala/Switch/SwitchNode.scala +++ /dev/null @@ -1,62 +0,0 @@ -package Switch - -import chisel3._ -import chisel3.util._ - - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -import MAC._ - - - -class SwitchNodeIO extends Bundle{ - val rx = Decoupled(new Mac_Stream_Bundle) - val mInfo = new Rx_MuxInfo_Bundle - - val tx = Flipped(Decoupled(new Mac_Stream_Bundle)) - -} - - - -abstract class SwitchNode(implicit p: Parameters) extends SwitchModule{ - val ex: SwitchNodeIO = IO(new SwitchNodeIO) - -} - - - -class MacNode(implicit p: Parameters) extends Mac{ - val rxBuff = Module(new RxBuff) - val txBuff = Module(new TxBuff) - - - - macTileLinkRx.io.rxEnq <> rxBuff.io.enq - txBuff.io.deq <> macTileLinkTx.io.txDeq - - rxBuff.io.deq <> ex.rx - ex.tx <> txBuff.io.enq - - - ex.mInfo <> rxBuff.mInfo -} - - - -class DmaNode(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMst(edgeOut){ - // def DmaMac = "habcdef".U(48.W) - - ex.tx <> txBuff.io.enq - rxBuff.io.deq <> ex.rx - - ex.mInfo.dest.valid := rxBuff.mInfo.dest.valid - ex.mInfo.dest.bits := 0.U - ex.mInfo.source.valid := rxBuff.mInfo.source.valid - ex.mInfo.source.bits := 0.U - -} - diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala deleted file mode 100644 index ef79442..0000000 --- a/src/main/scala/Switch/WithSwitch.scala +++ /dev/null @@ -1,49 +0,0 @@ -package Switch - -import chisel3._ - -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import org.chipsalliance.cde.config._ - - -trait WithSwitchMix { this: BaseSubsystem => - - val switch = LazyModule(new Switch) - - sbus.coupleFrom("switch_mst") { _ := TLBuffer() := TLWidthWidget(8 / 8) := switch.tlClientNode } - // pbus.coupleTo("switch_cfg") { switch0.tlMasterNode := TLFragmenter(pbus) := _ } - - for( i <- 0 until 3 ){ - pbus.coupleTo(s"mac_cfg$i") { switch.macReg(i).configNode := TLFragmenter(pbus) := _ } - ibus.fromSync := switch.macReg(i).int_node - } - - pbus.coupleTo("dma_cfg") { switch.dmaReg.configNode := TLFragmenter(pbus) := _ } - - - -} - - -trait WithSwitchMixModuleImp extends LazyModuleImp { - val outer: WithSwitchMix - - val switchIO = IO(new SwitchIO) - - switchIO <> outer.switch.module.io - - // println("Warning, did you delete the rocket-chip.jar on top to reflash?") - // println("Warning, did you delete the rocket-chip.jar on top to reflash?") - // println("Warning, did you delete the rocket-chip.jar on top to reflash?") - // println("Warning, did you delete the rocket-chip.jar on top to reflash?") - // println("Warning, did you delete the rocket-chip.jar on top to reflash?") - -} - -class SwitchConfig() extends Config((site, here, up) => { - case SwitchParamsKey => SwitchSetting() -}) - - diff --git a/src/main/scala/Switch/mac/MII.scala b/src/main/scala/Switch/mac/MII.scala deleted file mode 100644 index 96f2f71..0000000 --- a/src/main/scala/Switch/mac/MII.scala +++ /dev/null @@ -1,239 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - - - -class MIIMIO extends Bundle with MDIO{ - val Divider = Input( UInt(8.W) ) // Divider for the host clock // Divider (input clock will be divided by the Divider[7:0]) - val NoPre = Input(Bool()) // No Preamble (no 32-bit preamble) - - val WCtrlData = Input(Bool()) // Write Control Data operation - val CtrlData = Input( UInt(16.W) ) // Control Data (to be written to the PHY reg.) - - val Fiad = Input( UInt(5.W) ) // PHY Address - val Rgad = Input(UInt(5.W)) // Register Address (within the PHY) - - val RStat = Input( Bool() ) // Read Status operation - - val ScanStat = Input( Bool() ) // Scan Status operation - - val Busy = Output(Bool()) // Busy Signal - val LinkFail = Output(Bool()) // Link Integrity Signal - val Nvalid = Output(Bool()) // Invalid Status (qualifier for the valid scan result) - val Prsd = Output(UInt(16.W)) // Read Status Data (data read from the PHY) - - val WCtrlDataStart = Output(Bool()) // This signals resets the WCTRLDATA bit in the MIIM Command register - val RStatStart = Output(Bool()) // This signal resets the RSTAT BIT in the MIIM Command register - val UpdateMIIRX_DATAReg = Output(Bool()) // Updates MII RX_DATA register with read data - -} - -class MIIMBase extends Module{ - val io: MIIMIO = IO(new MIIMIO) - - - val ByteSelect = Wire( Vec( 4, Bool() ) ) // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. - - - // Counter counts half period - val Counter = RegInit( 1.U(8.W) ) - val mdc = RegInit(false.B) // Output clock - val mdcEn = (Counter === 0.U) & ~mdc // Enable signal is asserted for one Clk period before mdc rises. - val mdcEn_n = (Counter === 0.U) & mdc // Enable signal is asserted for one Clk period before mdc falls. - - val ShiftReg = RegInit(0.U(8.W)) // Shift register for shifting the data in and out - val Prsd = RegInit(0.U(16.W)) - val LinkFail = RegInit(false.B) - - - val BitCounter = RegInit( 0.U(7.W) ) // Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) - val EndOp = BitCounter === 63.U // Operation ends when the Bit Counter reaches 63 - - - val InProgress = RegInit(false.B) // Operation in progress - val InProgress_q = ShiftRegisters(InProgress, 3, false.B, mdcEn) // Operation in progress delayed 3 mdc cycles - val EndBusy = ShiftRegister(~InProgress_q(1) & InProgress_q(2), 2, false.B, true.B) // Generation of the EndBusy signal. It is used for ending the MII Management operation. - - val WriteOp = RegInit(false.B) // Write Operation Latch (When asserted, write operation is in progress) - - - - - io.mdc := mdc - io.LinkFail := LinkFail - io.Prsd := Prsd - - - - - -} - -/** Connecting the Clock Generator Module */ -trait MIIMClockGen{ this: MIIMBase => - - val TempDivider = Mux( io.Divider < 2.U, 2.U, io.Divider ) // If smaller than 2 - val CounterPreset = ( TempDivider >> 1 ) - 1.U // We are counting half of period - - when( Counter === 0.U ) { - mdc := ~mdc // mdc is asserted every other half period - Counter := CounterPreset - } .otherwise{ - Counter := Counter - 1.U - } - -} - - -trait MIIMShiftReg{ this: MIIMBase => - - val LatchByte0 = ShiftRegister(InProgress & ~WriteOp & BitCounter === "h3F".U, 2, false.B, mdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register - val LatchByte1 = ShiftRegister(InProgress & ~WriteOp & BitCounter === "h37".U, 2, false.B, mdcEn) // Latch Byte selects which part of Read Status Data is updated from the shift register - - ByteSelect(0) := InProgress & ((io.NoPre & (BitCounter === 0.U)) | (~io.NoPre & (BitCounter === "h20".U))); - ByteSelect(1) := InProgress & (BitCounter === "h28".U); - ByteSelect(2) := InProgress & WriteOp & (BitCounter === "h30".U); - ByteSelect(3) := InProgress & WriteOp & (BitCounter === "h38".U); - - when(mdcEn_n){ - when(ByteSelect.reduce(_|_)) { - ShiftReg := Mux1H(Seq( - ByteSelect(0) -> Cat("b01".U(2.W), ~WriteOp, WriteOp, io.Fiad(4,1)), - ByteSelect(1) -> Cat(io.Fiad.extract(0), io.Rgad(4,0), "b10".U(2.W)), - ByteSelect(2) -> io.CtrlData(15,8), - ByteSelect(3) -> io.CtrlData( 7,0), - )) - } .otherwise{ - ShiftReg := Cat(ShiftReg(6,0), io.mdi) - when(LatchByte0){ - Prsd := Cat(Prsd(15,8), ShiftReg(6,0), io.mdi) - when(io.Rgad === 1.U){ - LinkFail := ~ShiftReg.extract(1) // this is bit [2], because it is not shifted yet - } - } .elsewhen(LatchByte1){ - Prsd := Cat(ShiftReg(6,0), io.mdi, Prsd(7,0)) - } - } - } - -} - -trait MIIMOutputCtl{ this: MIIMBase => - - // Generation of the Serial Enable signal (enables the serialization of the data) - val SerialEn = ( WriteOp & InProgress & ( BitCounter > 31.U | ( ( BitCounter === 0.U ) & io.NoPre ) )) | - (~WriteOp & InProgress & (( BitCounter > 31.U & BitCounter < 46.U ) | ( ( BitCounter === 0.U ) & io.NoPre ))) - - val mdoEn = ShiftRegister( SerialEn | (InProgress & BitCounter<32.U), 3, false.B, mdcEn_n) - val mdo_2d = RegEnable( ~SerialEn & BitCounter<32.U, false.B, mdcEn_n) - val mdo_d = RegEnable( ShiftReg.extract(7) | mdo_2d, false.B, mdcEn_n) - val mdo = RegEnable( mdo_d, false.B, mdcEn_n) - io.mdo := mdo - io.mdoEn := mdoEn - -} - - -class MIIM extends MIIMBase with MIIMClockGen with MIIMShiftReg with MIIMOutputCtl{ - - val WCtrlData_q = ShiftRegisters(io.WCtrlData, 3, false.B, true.B) - val WCtrlDataStart = RegInit(false.B) // Start Write Control Data Command (positive edge detected) - val WCtrlDataStart_q = ShiftRegisters(WCtrlDataStart, 2, false.B, mdcEn) // Start Write Control Data Command delayed 2 mdc cycle - val WriteDataOp = WCtrlDataStart_q(0) & ~WCtrlDataStart_q(1) // Write Data Operation (positive edge detected) - io.WCtrlDataStart := WCtrlDataStart - - // Generation of the Operation signals - - - - val StartOp = Wire(Bool()) // Start Operation (start of any of the preceding operations) - - - - when( EndBusy ){ - WCtrlDataStart := false.B - } .elsewhen( WCtrlData_q(1) & ~WCtrlData_q(2) ){ - WCtrlDataStart := true.B - } - - // Update MII RX_DATA register - val WCtrlDataStart_q0 = RegEnable(WCtrlDataStart, false.B, ~EndBusy) - val UpdateMIIRX_DATAReg = RegNext(EndBusy & ~WCtrlDataStart_q0, false.B) // Updates MII RX_DATA register with read data - io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg - - - - val RStat_q = ShiftRegisters(io.RStat, 3, false.B, true.B) - val RStatStart = RegInit(false.B) // Start Read Status Command (positive edge detected) - val RStatStart_q = ShiftRegisters(RStatStart, 2, false.B, mdcEn) // Start Read Status Command delayed 2 mdc cycles - val ReadStatusOp = RStatStart_q(0) & ~RStatStart_q(1) // Read Status Operation (positive edge detected) - io.RStatStart := RStatStart - - when( EndBusy ){ - RStatStart := false.B - } .elsewhen(RStat_q(1) & ~RStat_q(2)){ - RStatStart := true.B - } - - - - - when(mdcEn){ - when(StartOp) { - InProgress := true.B - } .elsewhen(EndOp) { - InProgress := false.B - } - } - - - - val ScanStat_q = ShiftRegisters(io.ScanStat, 2, false.B, true.B) - val SyncStatmdcEn = RegEnable(ScanStat_q(1), false.B, mdcEn) // Scan Status operation delayed at least cycles and synchronized to mdcEn - val ScanStatusOp = SyncStatmdcEn & ~InProgress & ~InProgress_q(0) & ~InProgress_q(1) // Scan Status Operation (positive edge detected) - - - val Nvalid = RegInit(false.B) // Generation of the Nvalid signal (indicates when the status is invalid) - io.Nvalid := Nvalid - - when( ~InProgress_q(1) & InProgress_q(2) ) { - Nvalid := false.B - } .elsewhen(ScanStat_q(1) & ~SyncStatmdcEn) { - Nvalid := true.B - } - - - - - when(mdcEn){ - when(StartOp) { - when( ~InProgress ){ - WriteOp := Mux( WriteDataOp, true.B, false.B ) - } - } .elsewhen(EndOp) { - WriteOp := false.B - } - } - - - when( mdcEn ){ - when( InProgress ) { - when( io.NoPre & BitCounter === 0.U ) { - BitCounter := "h21".U - } .otherwise { - BitCounter := BitCounter + 1.U - } - } .otherwise { - BitCounter := 0.U - } - } - - - StartOp := WriteDataOp | ReadStatusOp | ScanStatusOp - io.Busy := io.WCtrlData | WCtrlDataStart | io.RStat | RStatStart | SyncStatmdcEn | EndBusy | InProgress | InProgress_q(2) | Nvalid - -} - - diff --git a/src/main/scala/Switch/mac/MacBundle.scala b/src/main/scala/Switch/mac/MacBundle.scala deleted file mode 100644 index 3907432..0000000 --- a/src/main/scala/Switch/mac/MacBundle.scala +++ /dev/null @@ -1,78 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - - - - -class TxBuffDesc extends Bundle{ - val len = UInt(16.W) //[31.16] - val rd = Bool() //[15] - val irq = Bool() //14 - val wr = Bool() //13 - val pad = Bool() //12 - val crc = Bool() //11 - val reserved1 = UInt(2.W) //10,9 - val ur = Bool() //8 - val rtry = UInt(4.W) //7 6 5 4 - val rl = Bool() //3 - val lc = Bool() //2 - val df = Bool() //1 - val cs = Bool() //0 -} - -class RxBuffDesc extends Bundle{ - val len = UInt(16.W) //[31.16] - val e = Bool() //15 - val irq = Bool() //14 - val wrap = Bool() //13 - val reserved1 = UInt(4.W) //12 11 10 9 - val cf = Bool() //8 - val m = Bool() //7 - val or = Bool() //6 - val is = Bool() //5 - val dn = Bool() //4 - val tl = Bool() //3 - val sf = Bool() //2 - val crc = Bool() //1 - val lc = Bool() //0 -} - -class MacWishboneMasterIO extends Bundle{ - val m_wb_adr_o = Output(UInt(32.W)) - val m_wb_sel_o = Output(UInt(4.W)) - val m_wb_we_o = Output(Bool()) - val m_wb_dat_i = Input(UInt(32.W)) - val m_wb_dat_o = Output(UInt(32.W)) - val m_wb_cyc_o = Output(Bool()) - val m_wb_stb_o = Output(Bool()) - val m_wb_ack_i = Input(Bool()) - val m_wb_err_i = Input(Bool()) - val m_wb_cti_o = Output(UInt(3.W)) - val m_wb_bte_o = Output(UInt(2.W)) -} - - -class MacWishboneSlaveIO extends Bundle{ - val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input - val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output - - val WB_ADR_I = Input(UInt(12.W)) // WISHBONE address input - val WB_WE_I = Input(Bool()) // WISHBONE write enable input - - val WB_SEL_I = Input(UInt(4.W)) // WISHBONE byte select input - val WB_CYC_I = Input(Bool()) // WISHBONE cycle input - val WB_STB_I = Input(Bool()) // WISHBONE strobe input - - val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output - val WB_ERR_O = Output(Bool()) // WISHBONE error output -} - -trait MDIO { this: Bundle => - val mdi = Input( Bool()) // MII Management Data In - val mdc = Output(Bool()) // MII Management Data Clock - val mdo = Output(Bool()) // MII Management Data Output - val mdoEn = Output(Bool()) // MII Management Data Output Enable -} - diff --git a/src/main/scala/Switch/mac/MacFifo.scala b/src/main/scala/Switch/mac/MacFifo.scala deleted file mode 100644 index 29c220a..0000000 --- a/src/main/scala/Switch/mac/MacFifo.scala +++ /dev/null @@ -1,77 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - -class MacFifoIO(dw: Int, cntw: Int) extends Bundle{ - val write = Input(Bool()) - val read = Input(Bool()) - val clear = Input(Bool()) - val data_in = Input(UInt(dw.W)) - - val data_out = Output(UInt(dw.W)) - val almost_full = Output(Bool()) - val full = Output(Bool()) - val almost_empty = Output(Bool()) - val empty = Output(Bool()) - val cnt = Output(UInt(cntw.W)) -} - -class MacFifo(dw: Int, dp: Int) extends Module{ - def cntw = log2Ceil(dp)+1 - val io: MacFifoIO = IO(new MacFifoIO(dw, cntw )) - - val fifo = Mem( dp, UInt(dw.W) ) - val data_out = Reg(UInt(dw.W)); io.data_out := data_out - - - - val cnt = RegInit( 0.U(cntw.W)); io.cnt := cnt - val read_pointer = RegInit(0.U(log2Ceil(dp).W)) - val write_pointer = RegInit(0.U(log2Ceil(dp).W)) - - when(io.clear){ - cnt := io.read ^ io.write - } .elsewhen(io.read ^ io.write){ - when(io.read){ - cnt := cnt - 1.U - } .otherwise{ - cnt := cnt + 1.U - } - } - - - when(io.clear){ - read_pointer := io.read - } .elsewhen(io.read & ~io.empty){ - read_pointer := read_pointer + 1.U - } - - - when(io.clear){ - write_pointer := io.write - } .elsewhen(io.write & ~io.full){ - write_pointer := write_pointer + 1.U - } - - io.empty := ~(cnt.orR) - io.almost_empty := cnt === 1.U - io.full := cnt === dp.U; - io.almost_full := cnt(cntw-2,0).andR - - - - when(io.write & io.clear){ - fifo.write(0.U, io.data_in) - } .elsewhen(io.write & ~io.full){ - fifo.write(write_pointer, io.data_in) - } - - - when(io.clear){ - data_out := fifo.read(0.U) - } .otherwise{ - data_out := fifo.read(read_pointer) - } - -} diff --git a/src/main/scala/Switch/mac/MacRx.scala b/src/main/scala/Switch/mac/MacRx.scala deleted file mode 100644 index 4fb534a..0000000 --- a/src/main/scala/Switch/mac/MacRx.scala +++ /dev/null @@ -1,298 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - - - -class MacRxIO extends Bundle{ - - val MRxDV = Input(Bool()) - val MRxD = Input(UInt(4.W)) - val Transmitting = Input(Bool()) - val r_IFG = Input(Bool()) - val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table - val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table - - val RxData = Output(UInt(8.W)) - val RxValid = Output(Bool()) - val RxStartFrm = Output(Bool()) - val RxEndFrm = Output(Bool()) - val ByteCnt = Output(UInt(16.W)) - val ByteCntEq0 = Output(Bool()) - val ByteCntGreat2 = Output(Bool()) - val CrcError = Output(Bool()) - val StateIdle = Output(Bool()) - val StatePreamble = Output(Bool()) - val StateSFD = Output(Bool()) - val StateData = Output(UInt(2.W)) -} - - -abstract class MacRxBase extends Module with RequireAsyncReset{ - val io: MacRxIO = IO(new MacRxIO) - - val MRxDEqD = io.MRxD === "hd".U - val MRxDEq5 = io.MRxD === "h5".U - - val IFGCounterEq24 = Wire(Bool()) - - val ByteCntEq0 = Wire(Bool()) - io.ByteCntEq0 := ByteCntEq0 - - val ByteCntEq1 = Wire(Bool()) - val ByteCntEq2 = Wire(Bool()) - val ByteCntEq3 = Wire(Bool()) - val ByteCntEq4 = Wire(Bool()) - val ByteCntEq5 = Wire(Bool()) - val ByteCntEq6 = Wire(Bool()) - val ByteCntEq7 = Wire(Bool()) - - val ByteCntSmall7 = Wire(Bool()) - - - val StateData0 = RegInit(false.B) - val StateData1 = RegInit(false.B) - val StateIdle = RegInit(false.B); io.StateIdle := StateIdle - val StateDrop = RegInit(true.B) - val StatePreamble = RegInit(false.B); io.StatePreamble := StatePreamble - val StateSFD = RegInit(false.B); io.StateSFD := StateSFD - - val RxData_d = RegInit(0.U(8.W)) - val RxData = RegNext(RxData_d, 0.U); io.RxData := RxData - - val Crc = RegInit("hFFFFFFFF".U(32.W)) - - - -} - -trait MacRxFSM { this: MacRxBase => - - val StateData = Cat( StateData1, StateData0 ) - io.StateData := StateData - - // Defining the next state - val StartIdle = ~io.MRxDV & (StateDrop | StatePreamble | StateSFD | StateData0 | StateData1 ) - val StartPreamble = io.MRxDV & ~MRxDEq5 & (StateIdle & ~io.Transmitting) - val StartSFD = io.MRxDV & MRxDEq5 & (StateIdle & ~io.Transmitting | StatePreamble) - val StartData0 = io.MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1) - val StartData1 = io.MRxDV & StateData0 - val StartDrop = io.MRxDV & ( - (StateIdle & io.Transmitting) | (StateSFD & ~IFGCounterEq24 & MRxDEqD ) - ) - - - when(StartPreamble | StartSFD | StartDrop){ - StateIdle := false.B - } .elsewhen( StartIdle ){ - StateIdle := true.B - } - - when( StartIdle ){ - StateDrop := false.B - } .elsewhen(StartDrop){ - StateDrop := true.B - } - - when(StartSFD | StartIdle | StartDrop ){ - StatePreamble := false.B - } .elsewhen(StartPreamble){ - StatePreamble := true.B - } - - when(StartPreamble | StartIdle | StartData0 | StartDrop){ - StateSFD := false.B - } .elsewhen (StartSFD){ - StateSFD := true.B - } - - - when(StartIdle | StartData1 | StartDrop){ - StateData0 := false.B - } .elsewhen(StartData0){ - StateData0 := true.B - } - - - when(StartIdle | StartData0 | StartDrop){ - StateData1 := false.B - } .elsewhen(StartData1){ - StateData1 := true.B - } - -} - -trait MacRxCounter { this: MacRxBase => - - val ByteCnt = RegInit(0.U(16.W)) - val IFGCounter = RegInit(0.U(5.W)) - - val ByteCntMax = ByteCnt === "hffff".U - - val ResetByteCounter = io.MRxDV & (io.StateSFD & MRxDEqD) - - val IncrementByteCounter = - ~ResetByteCounter & io.MRxDV & ( - io.StatePreamble | io.StateSFD | io.StateIdle & ~io.Transmitting | - (io.StateData.extract(1) & ~ByteCntMax) - ) - - val ByteCntDelayed = ByteCnt + 4.U - io.ByteCnt := ByteCnt - - - - - when( ResetByteCounter ){ - ByteCnt := 0.U - } .elsewhen(IncrementByteCounter){ - ByteCnt := ByteCnt + 1.U - } - - ByteCntEq0 := ByteCnt === 0.U - ByteCntEq1 := ByteCnt === 1.U - ByteCntEq2 := ByteCnt === 2.U - ByteCntEq3 := ByteCnt === 3.U - ByteCntEq4 := ByteCnt === 4.U - ByteCntEq5 := ByteCnt === 5.U - ByteCntEq6 := ByteCnt === 6.U - ByteCntEq7 := ByteCnt === 7.U - - io.ByteCntGreat2 := ByteCnt > 2.U - ByteCntSmall7 := ByteCnt < 7.U - - val ResetIFGCounter = io.StateSFD & io.MRxDV & MRxDEqD | StateDrop; - val IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | io.StateIdle | io.StatePreamble | io.StateSFD) & ~IFGCounterEq24; - - when( ResetIFGCounter ){ - IFGCounter := 0.U - } .elsewhen(IncrementIFGCounter){ - IFGCounter := IFGCounter + 1.U - } - - IFGCounterEq24 := (IFGCounter === "h18".U) | io.r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1 - -} - -trait MacRxFAddrCheck { this: MacRxBase => - - val HashBit = Wire(UInt(1.W)) - - val RxCheckEn = io.StateData.orR - - - - - - - val CrcHash = RegInit(0.U(6.W)) - val CrcHashGood = RegNext(StateData0 & ByteCntEq6) // Latching CRC for use in the hash table - - - - val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0) - val ByteHash = - Mux1H(Seq( - (CrcHash(4,3) === "b00".U) -> IntHash(7 ,0), - (CrcHash(4,3) === "b01".U) -> IntHash(15,8), - (CrcHash(4,3) === "b10".U) -> IntHash(23,16), - (CrcHash(4,3) === "b11".U) -> IntHash(31,24), - )) - - HashBit := ByteHash >> CrcHash(2,0) - - when(StateIdle){ - CrcHash := 0.U - } .elsewhen(StateData0 & ByteCntEq6){ - CrcHash := Crc(31,26) - } - -} - -trait MacRxCRC { this: MacRxBase => - - val Data_Crc = Cat(io.MRxD.extract(0),io.MRxD.extract(1),io.MRxD.extract(2),io.MRxD.extract(3)) - val Enable_Crc = io.MRxDV & (io.StateData.orR) - val Initialize_Crc = io.StateSFD - - when( Initialize_Crc ){ - Crc := "hFFFFFFFF".U - } .otherwise{ - Crc := Cat( - Crc.extract(27), - Crc.extract(26), - (Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(25), - (Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(24), - (Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(23), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(0) ^ Crc.extract(31) ^ Crc.extract(28))) ^ Crc.extract(22), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(31) ^ Crc.extract(30))) ^ Crc.extract(21), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(30) ^ Crc.extract(29))) ^ Crc.extract(20), - (Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(29) ^ Crc.extract(28))) ^ Crc.extract(19), - (Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(18), - Crc.extract(17), - Crc.extract(16), - (Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(15), - (Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(14), - (Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(13), - (Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(12), - (Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(11), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(10), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(9), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(8), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(7), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(6), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(5), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(4), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(3), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract( 2), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(1), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(0), - Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31)), - Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30)), - Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29)), - Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28)) - ) - } - - io.CrcError := Crc =/= "hc704dd7b".U // CRC not equal to magic number - - -} - -class MacRx extends MacRxBase with MacRxFSM with MacRxCounter with MacRxFAddrCheck with MacRxCRC{ - - - - val GenerateRxValid = StateData0 & ~ByteCntEq0; - val DelayData = RegNext(StateData0, false.B) - val LatchedByte = RegInit(0.U(8.W)) - when(true.B) { - LatchedByte := Cat(io.MRxD, LatchedByte(7,4))// Latched byte - } - - - - // Output byte stream - when( GenerateRxValid ){ - RxData_d := LatchedByte & Fill(8, StateData0 | StateData1) // Data goes through only in data state - } .elsewhen(~DelayData){ - RxData_d := 0.U // Delaying data to be valid for two cycles. // Zero when not active. - } - - - io.RxValid := ShiftRegister(GenerateRxValid, 2, false.B, true.B) - - - val GenerateRxStartFrm = StateData0 & ByteCntEq1 - - io.RxStartFrm := ShiftRegister(GenerateRxStartFrm, 2, false.B, true.B) - - - val GenerateRxEndFrm = StateData0 & (~io.MRxDV & io.ByteCntGreat2) - val DribbleRxEndFrm = StateData1 & ~io.MRxDV & io.ByteCntGreat2 - - val RxEndFrm_d = RegNext(GenerateRxEndFrm, false.B) - io.RxEndFrm := RegNext(RxEndFrm_d | DribbleRxEndFrm, false.B) - -} diff --git a/src/main/scala/Switch/mac/MacSRAM.scala b/src/main/scala/Switch/mac/MacSRAM.scala deleted file mode 100644 index cb4bf6c..0000000 --- a/src/main/scala/Switch/mac/MacSRAM.scala +++ /dev/null @@ -1,58 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - - -class MacSRAMIO extends Bundle{ - val we = Input(Vec(4, Bool())) // Write enable input, active high - val oe = Input(Bool()) // Output enable input, active high - val addr = Input(UInt(8.W)) // address bus inputs - val di = Input(UInt(32.W)) // input data bus - val dato = Output(UInt(32.W)) // output data bus -} - -class MacSRAM extends Module{ - val io: MacSRAMIO = IO(new MacSRAMIO) - - - // Generic RAM's registers and wires - - val mem0 = Mem( 256, UInt(8.W) ) - val mem1 = Mem( 256, UInt(8.W) ) - val mem2 = Mem( 256, UInt(8.W) ) - val mem3 = Mem( 256, UInt(8.W) ) - val q = Wire(UInt(32.W)) - val raddr = Reg( UInt(8.W) ) - - - // Data output drivers - io.dato := Mux((io.oe), q, DontCare) - - // read operation - when( true.B ){ - raddr := io.addr // read address needs to be registered to read clock - } - - q := Mux(reset.asBool, 0.U, Cat(mem3.read(raddr), mem2.read(raddr), mem1.read(raddr), mem0.read(raddr))) - - // write operation - when(io.we(3)){ - mem3.write(io.addr, io.di(31,24)) - } - - when(io.we(2)){ - mem2.write(io.addr, io.di(23,16)) - } - - when(io.we(1)){ - mem1.write(io.addr, io.di(15, 8)) - } - - when(io.we(0)){ - mem0.write(io.addr, io.di( 7, 0)) - } - - -} - diff --git a/src/main/scala/Switch/mac/MacStatus.scala b/src/main/scala/Switch/mac/MacStatus.scala deleted file mode 100644 index e955ab1..0000000 --- a/src/main/scala/Switch/mac/MacStatus.scala +++ /dev/null @@ -1,128 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - -class MacStatusIO extends Bundle{ - val asyncReset = Input(AsyncReset()) - - val MRxClk = Input(Bool()) - val RxCrcError = Input(Bool()) - val MRxDV = Input(Bool()) - val RxStateSFD = Input(Bool()) - val RxStateData = Input(UInt(2.W)) - val RxStatePreamble = Input(Bool()) - val RxStateIdle = Input(Bool()) - val Transmitting = Input(Bool()) - val RxByteCnt = Input(UInt(16.W)) - val RxByteCntEq0 = Input(Bool()) - val RxByteCntGreat2 = Input(Bool()) - val MRxD = Input(UInt(4.W)) - val Collision = Input(Bool()) - val CollValid = Input(UInt(6.W)) - val StartTxDone = Input(Bool()) - val StartTxAbort = Input(Bool()) - val MTxClk = Input(Bool()) - val MaxCollisionOccured = Input(Bool()) - val LateCollision = Input(Bool()) - val DeferIndication = Input(Bool()) - val TxStartFrm = Input(Bool()) - val StatePreamble = Input(Bool()) - val StateData = Input(UInt(2.W)) - val CarrierSense = Input(Bool()) - val Loopback = Input(Bool()) - val r_FullD = Input(Bool()) - val RstDeferLatched = Input(Bool()) - - val LatchedCrcError = Output(Bool()) - val RxLateCollision = Output(Bool()) - val DribbleNibble = Output(Bool()) - val LoadRxStatus = Output(Bool()) - val RetryLimit = Output(Bool()) - val LateCollLatched = Output(Bool()) - val DeferLatched = Output(Bool()) - val CarrierSenseLost = Output(Bool()) -} - -class MacStatus extends RawModule{ - val io: MacStatusIO = IO(new MacStatusIO) - - withClockAndReset( io.MRxClk.asClock, io.asyncReset ) { - - val LatchedCrcError = RegInit(false.B); io.LatchedCrcError := LatchedCrcError // Crc error - - when(io.RxStateSFD){ - LatchedCrcError := false.B - } .elsewhen(io.RxStateData.extract(0)){ - LatchedCrcError := io.RxCrcError & ~io.RxByteCntEq0; - } - - - // Time to take a sample - val TakeSample = - (io.RxStateData.orR & ~io.MRxDV) - - val LoadRxStatus = RegNext(TakeSample, false.B); io.LoadRxStatus := LoadRxStatus // LoadRxStatus - - - - - val RxLateCollision = RegInit(false.B); io.RxLateCollision := RxLateCollision // Late Collision - val RxColWindow = RegInit(true.B)// Collision Window - - when(LoadRxStatus){ - RxLateCollision := false.B - } .elsewhen(io.Collision & (~io.r_FullD) ){ - RxLateCollision := true.B - } - - when(~io.Collision & io.RxByteCnt(5,0) === io.CollValid & io.RxStateData.extract(1)){ - RxColWindow := false.B - } .elsewhen(io.RxStateIdle){ - RxColWindow := true.B - } - - - - - // DribbleNibble - val DribbleNibble = RegInit(false.B); io.DribbleNibble := DribbleNibble - - when(io.RxStateSFD){ - DribbleNibble := false.B - } .elsewhen(~io.MRxDV & io.RxStateData.extract(1)){ - DribbleNibble := true.B - } - - } - - - - withClockAndReset( io.MTxClk.asClock, io.asyncReset ) { - val RetryLimit = RegEnable( io.MaxCollisionOccured, false.B, io.StartTxDone | io.StartTxAbort ); io.RetryLimit := RetryLimit // Latched Retransmission limit - val LateCollLatched = RegEnable( io.LateCollision, false.B, io.StartTxDone | io.StartTxAbort); io.LateCollLatched := LateCollLatched // Latched Late Collision - - - val DeferLatched = RegInit(false.B); io.DeferLatched := DeferLatched // Latched Defer state - - when(io.DeferIndication){ - DeferLatched := true.B - } .elsewhen(io.RstDeferLatched){ - DeferLatched := false.B - } - - val CarrierSenseLost = RegInit(false.B); io.CarrierSenseLost := CarrierSenseLost // CarrierSenseLost - - when((io.StatePreamble | io.StateData.orR) & ~io.CarrierSense & ~io.Loopback & ~io.Collision & ~io.r_FullD){ - CarrierSenseLost := true.B - } .elsewhen(io.TxStartFrm){ - CarrierSenseLost := false.B - } - - - - - } -} - - diff --git a/src/main/scala/Switch/mac/MacTileLinkRx.scala b/src/main/scala/Switch/mac/MacTileLinkRx.scala deleted file mode 100644 index 46a5b13..0000000 --- a/src/main/scala/Switch/mac/MacTileLinkRx.scala +++ /dev/null @@ -1,232 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - -import freechips.rocketchip.util._ - - -class Mac_Stream_Bundle extends Bundle{ - val data = UInt(8.W) - val isStart = Bool() - val isLast = Bool() -} - - - -class MacTileLinkRxIO extends Bundle{ - - val LoadRxStatus = Input(Bool()) - - val RxData = Input(UInt(8.W)) // Received data byte (from PHY) - val RxValid = Input(Bool()) - val RxStartFrm = Input(Bool()) - val RxEndFrm = Input(Bool()) - - val DribbleNibble = Input(Bool()) - val LatchedCrcError = Input(Bool()) - val RxLateCollision = Input(Bool()) - - val asyncReset = Input(AsyncReset()) - val MRxClk = Input(Bool()) - - val Busy_IRQ = Output(Bool()) - - - val r_RxEn = Input(Bool()) // Receive enable - - - - val rxEnq = Decoupled(new Mac_Stream_Bundle) - - - -} - - -class MacTileLinkRx extends Module{ - val io = IO(new MacTileLinkRxIO) - - val syncReqBundle = Wire(Decoupled(new Mac_Stream_Bundle)) - val asyncReqBundle = Wire(Decoupled(new Mac_Stream_Bundle)) - val req_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle)) - - val rxReady = RegInit(false.B) - val rxReadyAsync = Wire(Bool()) - withClockAndReset( io.MRxClk.asClock, io.asyncReset ) { - rxReadyAsync := ShiftRegister( rxReady, 2, false.B, true.B ) - } - - - withClockAndReset(io.MRxClk.asClock, io.asyncReset){ - - when( io.LoadRxStatus ) { - when( io.DribbleNibble ) { printf("Warning! DribbleNibble!\n"); } - when( io.LatchedCrcError ) { printf("Warning! LatchedCrcError!\n"); } - when( io.RxLateCollision ) { printf("Warning! RxLateCollision!\n"); } - } - - val RxEnableWindow = RegInit(false.B) - - - - - // Indicating start of the reception process - val SetWriteRxDataToFifo = - io.RxValid & rxReadyAsync & (io.RxStartFrm | RxEnableWindow ) - - - // Generation of the end-of-frame signal - when(io.RxStartFrm){ - RxEnableWindow := true.B - } .elsewhen(io.RxEndFrm ){ - RxEnableWindow := false.B - } - - - - - - - val rxFifo = Module(new Queue(new Mac_Stream_Bundle, 4)) - rxFifo.io.enq.valid := SetWriteRxDataToFifo - rxFifo.io.enq.bits.data := io.RxData - rxFifo.io.enq.bits.isStart := io.RxStartFrm - rxFifo.io.enq.bits.isLast := io.RxEndFrm - assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) ) - - asyncReqBundle <> rxFifo.io.deq - - - } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - syncReqBundle <> FromAsyncBundle( req_ToAsync ) - - withClockAndReset(io.MRxClk.asClock, io.asyncReset) { - req_ToAsync <> ToAsyncBundle( asyncReqBundle ) - } - - - - - - - - - - - - // Busy Interrupt - val Busy_IRQ_rck = withClockAndReset(io.MRxClk.asClock, io.asyncReset) {RegInit(false.B)} - val Busy_IRQ_sync = ShiftRegister(Busy_IRQ_rck, 2, false.B, true.B) - - - io.Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B) - - - withClockAndReset( io.MRxClk.asClock, io.asyncReset ) { - val Busy_IRQ_syncb = ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B ) - - when(io.RxValid & io.RxStartFrm & ~rxReadyAsync){ - Busy_IRQ_rck := true.B - } .elsewhen(Busy_IRQ_syncb){ - Busy_IRQ_rck := false.B - } - - } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - when(syncReqBundle.bits.isLast & syncReqBundle.fire ){ - rxReady := false.B - } .elsewhen( io.r_RxEn & (io.rxEnq.ready) ){ - rxReady := true.B - } - - - io.rxEnq.bits := syncReqBundle.bits - io.rxEnq.valid := syncReqBundle.valid - syncReqBundle.ready := io.rxEnq.ready - - - - assert( ~(io.rxEnq.valid & ~io.rxEnq.ready), "Assert Failed, rx overrun!" ) - - - - - - - - - - - - - -} - - - diff --git a/src/main/scala/Switch/mac/MacTileLinkTx.scala b/src/main/scala/Switch/mac/MacTileLinkTx.scala deleted file mode 100644 index fda20fd..0000000 --- a/src/main/scala/Switch/mac/MacTileLinkTx.scala +++ /dev/null @@ -1,238 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - - -import freechips.rocketchip.util._ - - -class MacTileLinkTxIO extends Bundle{ - - - - val RstDeferLatched = Output(Bool()) - - val TxStartFrm = Output(Bool()) // Transmit packet start frame - val TxEndFrm = Output(Bool()) // Transmit packet end frame - val TxData = Output(UInt(8.W)) // Transmit packet data byte - - val TxUsedData = Input(Bool()) // Transmit packet used data - val TxAbort = Input(Bool()) // Transmit packet abort - val TxDone = Input(Bool()) // Transmission ended - - val MTxClk = Input(Bool()) - val asyncReset = Input(AsyncReset()) - - - - // Tx Status signals - val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made) - val LateCollLatched = Input(Bool()) // Late collision occured - val DeferLatched = Input(Bool()) // Defer indication (Frame was defered before sucessfully sent) - val CarrierSenseLost = Input(Bool()) // Carrier Sense was lost during the frame transmission - val PerPacketCrcEn = Output(Bool()) // Per packet crc enable - - //Register - val r_TxEn = Input(Bool()) // Transmit enable - - val txDeq = Flipped(Decoupled(new Mac_Stream_Bundle)) - - val isTxIdle = Input(Bool()) - -} - - - -class MacTileLinkTx extends Module{ - val io = IO(new MacTileLinkTxIO) - - val syncReqBundle = Wire(Decoupled(new Mac_Stream_Bundle)) - val asyncReqBundle = Wire(Decoupled(new Mac_Stream_Bundle)) - val txReq_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle)) - - - - withClockAndReset( io.MTxClk.asClock, io.asyncReset ){ - - - - val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm - val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm - val TxData = RegInit(0.U(8.W)); io.TxData := TxData - - // Generating delayed signals - val TxAbort_q = RegNext( io.TxAbort, false.B) - val TxUsedData_q = RegNext( io.TxUsedData, false.B) - - // Changes for tx occur every second clock. Flop is used for this manner. - val Flop = RegInit(false.B) - when( io.TxDone | io.TxAbort){ - Flop := false.B - } .elsewhen ( io.TxUsedData ){ - Flop := ~Flop - } - - when( asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm & io.isTxIdle ){ - TxStartFrm := true.B - } .elsewhen(TxUsedData_q | io.TxAbort & (~TxAbort_q) ){ - TxStartFrm := false.B - } - - - - // Tx end frame generation - when(Flop & TxEndFrm | io.TxAbort){ - TxEndFrm := false.B - } .elsewhen( asyncReqBundle.fire & asyncReqBundle.bits.isLast ){ - TxEndFrm := true.B - } - - - - asyncReqBundle.ready := - asyncReqBundle.valid & asyncReqBundle.bits.isStart & ~TxStartFrm & io.isTxIdle | - io.TxUsedData & Flop & ~TxEndFrm | - TxStartFrm & io.TxUsedData & Flop - - when( asyncReqBundle.fire ){ - TxData := asyncReqBundle.bits.data - } - - - assert( ~(asyncReqBundle.ready & ~asyncReqBundle.valid) ) - - - - } - - - - - - - - - - - - - - - - - txReq_ToAsync <> ToAsyncBundle( syncReqBundle ) - withClockAndReset(io.MTxClk.asClock, io.asyncReset) { - asyncReqBundle <> FromAsyncBundle( txReq_ToAsync ) - } - - val BlockingTxStatusWrite = RegInit(false.B) - - withClockAndReset( io.MTxClk.asClock, io.asyncReset ){ - val BlockingTxStatusWrite_sync = ShiftRegister( BlockingTxStatusWrite, 2, false.B, true.B) - io.RstDeferLatched := BlockingTxStatusWrite_sync & ~RegNext(BlockingTxStatusWrite_sync, false.B) - } - - - - val TxAbortSync = ShiftRegister( io.TxAbort, 2, false.B, true.B ) - val TxDoneSync = ShiftRegister( io.TxDone, 2, false.B, true.B ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - val txDonePulse = TxDoneSync & ~RegNext(TxDoneSync, false.B) - val txAbortPulse = TxAbortSync & ~RegNext(TxAbortSync, false.B) - - - io.PerPacketCrcEn := false.B - - - - - when( txDonePulse | txAbortPulse ){ - - when(io.RetryLimit) {printf("Warning, io.RetryLimit\n")} - when(io.LateCollLatched) {printf("Warning, io.LateCollLatched\n")} - when(io.DeferLatched) {printf("Warning, io.DeferLatched\n")} - when(io.CarrierSenseLost) {printf("Warning, io.CarrierSenseLost\n")} - when(txAbortPulse) {printf("Warning, txAbortPulse\n")} - } - - val killTrans = RegInit(false.B) - - when( (io.txDeq.fire & io.txDeq.bits.isLast) | ~io.txDeq.valid ){ - killTrans := false.B - } .elsewhen( txAbortPulse ){ - killTrans := true.B - } - - - - - - - val isTxEnable = RegInit(false.B) - - - - when( io.txDeq.fire & io.txDeq.bits.isLast & ~io.r_TxEn ){ - isTxEnable := false.B - } .elsewhen( io.r_TxEn ){ - isTxEnable := true.B - } - - - io.txDeq.ready := Mux( killTrans, true.B, isTxEnable & syncReqBundle.ready ) - syncReqBundle.valid := Mux( killTrans, false.B, isTxEnable & io.txDeq.valid ) - syncReqBundle.bits := io.txDeq.bits - - - - - - - - - - - - when(~TxDoneSync & ~TxAbortSync){ - BlockingTxStatusWrite := false.B - } .elsewhen(txDonePulse | txAbortPulse){ - BlockingTxStatusWrite := true.B - } - - - - - - -} - diff --git a/src/main/scala/Switch/mac/MacTx.scala b/src/main/scala/Switch/mac/MacTx.scala deleted file mode 100644 index c37f12c..0000000 --- a/src/main/scala/Switch/mac/MacTx.scala +++ /dev/null @@ -1,399 +0,0 @@ -package MAC - -import chisel3._ -import chisel3.util._ - - -class MacTxIO extends Bundle{ - - val TxStartFrm = Input(Bool()) // Transmit packet start frame - val TxEndFrm = Input(Bool()) // Transmit packet end frame - val TxData = Input(UInt(8.W)) // Transmit packet data byte - val CarrierSense = Input(Bool()) // Carrier sense (synchronized) - val Collision = Input(Bool()) // Collision (synchronized) - - val CrcEn = Input(Bool()) // Crc enable (from register) - val FullD = Input(Bool()) // Full duplex (from register) - val IPGT = Input(UInt(7.W)) // Back to back transmit inter packet gap parameter (from register) - val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register) - val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register) - val CollValid = Input(UInt(6.W)) // Valid collision window (from register) - val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register) - - val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY) - val MTxEn = Output(Bool()) // Transmit enable (to PHY) - val TxDone = Output(Bool()) // Transmit packet done (to RISC) - val TxAbort = Output(Bool()) // Transmit packet abort (to RISC) - val TxUsedData = Output(Bool()) // Transmit packet used data (to RISC) - val WillTransmit = Output(Bool()) // Will transmit (to RxEthMAC) - val ResetCollision = Output(Bool()) // Reset Collision (for synchronizing collision) - val StartTxDone = Output(Bool()) - val StartTxAbort = Output(Bool()) - val MaxCollisionOccured= Output(Bool()) - val LateCollision = Output(Bool()) - val DeferIndication = Output(Bool()) - val StatePreamble = Output(Bool()) - val StateData = Output(UInt(2.W)) - - val isTxIdle = Output(Bool()) -} - -abstract class MacTxBase extends Module with RequireAsyncReset{ - val io: MacTxIO = IO(new MacTxIO) - - - - - val StartIPG = Wire(Bool()) - val StartPreamble = Wire(Bool()) - val StartData = Wire( Vec(2,Bool())) - val StartFCS = Wire(Bool()) - val StartJam = Wire(Bool()) - val StartDefer = Wire(Bool()) - - - - - val StateSFD = Wire(Bool()) - - val CrcError = Wire(Bool()) - - - val NibbleMinFl = Wire(Bool()) - val ExcessiveDefer = Wire(Bool()) - - val StateIPG = RegInit(false.B) - val StateIdle = RegInit(false.B) - val StatePreamble = RegInit(false.B); io.StatePreamble := StatePreamble - val StateData = RegNext( Cat(StartData(1), StartData(0)), 0.U(2.W)); io.StateData := StateData - val StatePAD = RegInit(false.B) - val StateFCS = RegInit(false.B) - val StateJam = RegInit(false.B) - val StateJam_q = RegNext(StateJam, false.B) - val StateDefer = RegInit(true.B) - val Rule1 = RegInit(false.B) - - val ColWindow = RegInit(true.B) - val PacketFinished_q = RegInit(false.B) - val ByteCnt = RegInit(0.U(16.W)) // Transmit Byte Counter - val NibCnt = RegInit(0.U(16.W)) // Nibble Counter - val NibCntEq7 = NibCnt === 7.U - val NibCntEq15 = NibCnt === 15.U - - io.isTxIdle := StateIdle -} - - - -trait MacTxFSM { this: MacTxBase => - - // Defining the next state - StartIPG := StateDefer & ~ExcessiveDefer & ~io.CarrierSense - - val StartIdle = StateIPG & (Rule1 & NibCnt(6,0) >= io.IPGT | ~Rule1 & NibCnt(6,0) >= io.IPGR2) - - StartPreamble := StateIdle & io.TxStartFrm & ~io.CarrierSense - - StartData(0) := ~io.Collision & (StatePreamble & NibCntEq15 | StateData(1) & ~io.TxEndFrm) - StartData(1) := ~io.Collision & StateData(0) - - val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & ~NibbleMinFl - - StartFCS := - (~io.Collision & StateData(1) & io.TxEndFrm & NibbleMinFl & io.CrcEn) | - (~io.Collision & StatePAD & NibbleMinFl & io.CrcEn) - - StartJam := (io.Collision ) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS) - - StartDefer := - (StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2) | - (StateIdle & io.CarrierSense) | - (StateJam & NibCntEq7) | - io.StartTxDone - - io.DeferIndication := StateIdle & io.CarrierSense - - - - when(StartDefer | StartIdle){ - StateIPG := false.B - }.elsewhen(StartIPG){ - StateIPG := true.B - } - - when(StartDefer | StartPreamble){ - StateIdle := false.B - }.elsewhen(StartIdle){ - StateIdle := true.B - } - - when(StartData(0) | StartJam){ - StatePreamble := false.B - } .elsewhen(StartPreamble){ - StatePreamble := true.B - } - - when(StartFCS | StartJam | StartDefer){ - StatePAD := false.B - }.elsewhen(StartPAD){ - StatePAD := true.B - } - - when(StartJam | StartDefer){ - StateFCS := false.B - } .elsewhen(StartFCS){ - StateFCS := true.B - } - - when(StartDefer){ - StateJam := false.B - } .elsewhen(StartJam){ - StateJam := true.B - } - - when(StartIPG){ - StateDefer := false.B - } .elsewhen(StartDefer){ - StateDefer := true.B - } - - // This sections defines which interpack gap rule to use - when(StateIdle){ - Rule1 := false.B - } .elsewhen(StatePreamble | io.FullD){ - Rule1 := true.B - } - - -} - -trait MacTxCounter { this: MacTxBase => - - val ByteCntMax = Wire(Bool()) - - val IncrementNibCnt = - StateIPG | StatePreamble | - (StateData(1) | StateData(0)) | - StatePAD | StateFCS | StateJam | - (StateDefer & ~ExcessiveDefer & io.TxStartFrm) - - - val ResetNibCnt = - (StateDefer & ExcessiveDefer & ~io.TxStartFrm) | - (StatePreamble & NibCntEq15) | - (StateJam & NibCntEq7) | - StateIdle | StartDefer | StartIPG | StartFCS | StartJam - - - when(ResetNibCnt){ - NibCnt := 0.U - } .elsewhen(IncrementNibCnt){ - NibCnt := NibCnt + 1.U - } - - NibbleMinFl := NibCnt >= (((64.U-4.U)<<1) - 1.U) // FCS should not be included in NibbleMinFl - - ExcessiveDefer := NibCnt(13,0) === "h17b7".U & ~io.ExDfrEn; // 6071 nibbles - - val IncrementByteCnt = - (StateData(1) & ~ByteCntMax) | - ((StatePAD | StateFCS) & NibCnt.extract(0) & ~ByteCntMax) - - val ResetByteCnt = - (StateIdle & io.TxStartFrm) | - PacketFinished_q - - - ByteCntMax := ByteCnt.andR - when(ResetByteCnt){ - ByteCnt := 0.U - } .elsewhen(IncrementByteCnt){ - ByteCnt := ByteCnt + 1.U - } - - -} - - - -trait MacTxCRC{ this: MacTxBase => - - val Initialize_Crc = StateIdle | StatePreamble - val Enable_Crc = ~StateFCS - - val Data_Crc = - Mux1H(Seq( - StateData(0) -> Cat( io.TxData(0), io.TxData(1), io.TxData(2), io.TxData(3) ), - StateData(1) -> Cat( io.TxData(4), io.TxData(5), io.TxData(6), io.TxData(7) ), - )) - - val Crc = RegInit("hFFFFFFFF".U(32.W)) - - when( Initialize_Crc ){ - Crc := "hFFFFFFFF".U - } .otherwise{ - Crc := Cat( - Crc.extract(27), - Crc.extract(26), - (Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(25), - (Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(24), - (Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(23), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(0) ^ Crc.extract(31) ^ Crc.extract(28))) ^ Crc.extract(22), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(31) ^ Crc.extract(30))) ^ Crc.extract(21), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(30) ^ Crc.extract(29))) ^ Crc.extract(20), - (Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(29) ^ Crc.extract(28))) ^ Crc.extract(19), - (Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(18), - Crc.extract(17), - Crc.extract(16), - (Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(15), - (Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(14), - (Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(13), - (Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(12), - (Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(11), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(10), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(9), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(8), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(7), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(6), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(5), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(4), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(3), - (Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract( 2), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(1), - (Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(0), - Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31)), - Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30)), - Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29)), - Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28)) - ) - } - - CrcError := Crc =/= "hc704dd7b".U // CRC not equal to magic number - - -} - -class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC { - val MTxD = RegInit(0.U(4.W)); io.MTxD := MTxD - val StopExcessiveDeferOccured = RegInit(false.B) - - val StatusLatch = RegInit(false.B) - val TxUsedData = RegNext(StartData(0) | StartData(1), false.B); io.TxUsedData := TxUsedData - val TxDone = RegInit(false.B); io.TxDone := ~io.TxStartFrm & TxDone - val TxAbort = RegInit(false.B); io.TxAbort := ~io.TxStartFrm & TxAbort - - val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn - - val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit - - - - io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS) - val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured - - io.StartTxDone := - ~io.Collision & - ( (StateFCS & NibCntEq7) | - (StateData(1) & io.TxEndFrm & NibbleMinFl & ~io.CrcEn) | - (StatePAD & NibbleMinFl & ~io.CrcEn) ) - - io.LateCollision := StartJam & ~ColWindow - io.MaxCollisionOccured := StartJam & ColWindow; - StateSFD := StatePreamble & NibCntEq15; - io.StartTxAbort := ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured - - when(~io.TxStartFrm){ - StopExcessiveDeferOccured := false.B - }.elsewhen(ExcessiveDeferOccured){ - StopExcessiveDeferOccured := true.B - } - - - // Collision Window - when(~io.Collision & ByteCnt(5,0) === io.CollValid & (StateData(1) | StatePAD & NibCnt.extract(0) | StateFCS & NibCnt.extract(0))){ - ColWindow := false.B - } .elsewhen(StateIdle | StateIPG){ - ColWindow := true.B - } - - - - - // Start Window - when(~io.TxStartFrm){ - StatusLatch := false.B - } .elsewhen(ExcessiveDeferOccured | StateIdle){ - StatusLatch := true.B - } - - - // Transmit packet done - when(io.TxStartFrm & ~StatusLatch){ - TxDone := false.B - }.elsewhen(io.StartTxDone){ - TxDone := true.B - } - - - // Transmit packet abort - when(io.TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured){ - TxAbort := false.B - } .elsewhen(io.StartTxAbort){ - TxAbort := true.B - } - - - when( true.B ){ - MTxD := // Transmit nibble - Mux( - StateData(0), io.TxData(3,0), // Lower nibble - Mux(StateData(1), io.TxData(7,4), // Higher nibble - Mux( StateFCS, Cat(~Crc.extract(28), ~Crc.extract(29), ~Crc.extract(30), ~Crc.extract(31)), // Crc - Mux(StateJam, 9.U, // Jam pattern - Mux( - StatePreamble, Mux(NibCntEq15, "hd".U, 5.U),// SFD,Preamble - 0.U - ) - ) - ) - ) - ) - } - - val PacketFinished_d = io.StartTxDone | io.LateCollision | io.MaxCollisionOccured | ExcessiveDeferOccured; - val PacketFinished = RegNext(PacketFinished_d, false.B) - when(true.B){ - PacketFinished_q := PacketFinished - } - -} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/src/main/scala/Wrapper/Efabless.scala b/src/main/scala/Wrapper/Efabless.scala deleted file mode 100644 index 4a6e99b..0000000 --- a/src/main/scala/Wrapper/Efabless.scala +++ /dev/null @@ -1,136 +0,0 @@ -package Wrapeer - -import chisel3._ -import chisel3.util._ -import chisel3.experimental.dataview._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ - -import MAC._ -import Switch._ - - - -class EfablessTopIO(implicit p: Parameters) extends SwitchIO{ - - val wbs_stb_i = Input(Bool()) - val wbs_cyc_i = Input(Bool()) - val wbs_we_i = Input(Bool()) - val wbs_sel_i = Input(UInt(4.W)) - val wbs_dat_i = Input(UInt(32.W)) - val wbs_adr_i = Input(UInt(32.W)) - val wbs_ack_o = Output(Bool()) - val wbs_dat_o = Output(UInt(32.W)) - -} - -class EfablessTop(implicit p: Parameters) extends LazyModule with HasSwitchParameters{ - - - - val eSwitch = LazyModule(new Switch) - - - val wbCnvMasterNode = TLClientNode(Seq(TLMasterPortParameters.v1( - Seq(TLMasterParameters.v1( - name = "wishbone", - sourceId = IdRange(0, 1), - )) - ))) - - val sram = TLRAM( - address = AddressSet(0x30002000L, 0x00001fffL), - cacheable = false, - executable = false, - atomics = false, - beatBytes = 4 - ) - - val wbXbar = TLXbar() - val sramXbar = TLXbar() - - eSwitch.macReg(0).configNode := TLBuffer() := wbXbar - eSwitch.macReg(1).configNode := TLBuffer() := wbXbar - eSwitch.dmaReg.configNode := TLBuffer() := wbXbar - sram := TLBuffer() := sramXbar := TLBuffer() := wbXbar := TLBuffer() := wbCnvMasterNode - sramXbar := TLBuffer() := eSwitch.tlClientNode - - - val intSinkNode = for( i <- 0 until chn ) yield { IntSinkNode(IntSinkPortSimple()) } - intSinkNode(0) := eSwitch.macReg(0).int_node - intSinkNode(1) := eSwitch.macReg(1).int_node - - val int0 = InModuleBody { - intSinkNode(0).makeIOs() - } - - val int1 = InModuleBody { - intSinkNode(1).makeIOs() - } - - lazy val module = new EfablessTopImp(this) -} - - -class EfablessTopImp(outer: EfablessTop)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{ - val io: EfablessTopIO = IO(new EfablessTopIO) - - io.viewAsSupertype(new SwitchIO) <> outer.eSwitch.module.io - - val ( wb_bus, wb_edge ) = outer.wbCnvMasterNode.out.head - - - val wbAck = RegInit(false.B) - val wbDato = Reg(UInt(32.W)) - - val isBusy = RegInit(false.B) - val wbAValid = RegInit(false.B) - val wbABits = Reg(new TLBundleA(wb_edge.bundle)) - - when( io.wbs_cyc_i & io.wbs_stb_i & ~isBusy ){ - assert( ~wbAValid ) - wbAValid := true.B - isBusy := true.B - when( io.wbs_we_i ){ - wbABits := - wb_edge.Put( - fromSource = 0.U, - toAddress = io.wbs_adr_i, - lgSize = log2Ceil(32/8).U, - data = io.wbs_dat_i, - mask = io.wbs_sel_i, - )._2 - } .otherwise{ - wbABits := - wb_edge.Get( - fromSource = 0.U, - toAddress = io.wbs_adr_i, - lgSize = log2Ceil(32/8).U, - )._2 - } - } .elsewhen( wb_bus.a.fire ){ - wbAValid := false.B - } .elsewhen( wb_bus.d.fire ){ - wbAck := true.B - wbDato := wb_bus.d.bits.data - } .elsewhen( (~io.wbs_cyc_i | ~io.wbs_stb_i) & isBusy ){ - isBusy := false.B - wbAck := false.B - } - - - wb_bus.d.ready := true.B - wb_bus.a.valid := wbAValid - wb_bus.a.bits := wbABits - - io.wbs_ack_o := wbAck & io.wbs_cyc_i & io.wbs_stb_i - io.wbs_dat_o := wbDato -} - - - - - diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index a9557f7..2f3648d 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -8,11 +8,11 @@ import chisel3.util._ class CDRInIO extends Bundle{ val axis = Decoupled(new AXIS_Bundle(8)) val serDat = Input(Bool()) - + val flush = Input(Bool()) } -abstract class CDRInBase extends Module{ +abstract class CDRInBase extends Module with RequireAsyncReset{ val io: CDRInIO = IO(new CDRInIO) @@ -21,48 +21,6 @@ abstract class CDRInBase extends Module{ val syncSerDat = Wire(Bool()) } -trait CDRInOverSample{ this: CDRInBase => - - val overCLK = IO(Input(Bool())) - val sampleRate: Int = 4 - require(sampleRate >= 4) - - val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) } - - val flitReg = for( i <- 0 until sampleRate ) yield { - withClockAndReset(overCLK.asClock, reset.asBool){ - RegNext( - (sampleReg(i) & sampleReg(i+1)) | - (sampleReg(i) & sampleReg(i+2)) | - (sampleReg(i+1) & sampleReg(i+2)), false.B - ) - } - } - - val arbCnt = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } - arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) - val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } - withClockAndReset(overCLK.asClock, reset.asBool){ - when( flitReg(0) ^ flitReg(1) ){ - arbLock := arbCnt - } - - - } - - val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext( - Mux1H( - (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield { - //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 - ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate) - }) - ) - )} - - - syncSerDat := ShiftRegister( asyncSerDat, 2 ) - -} trait CDRInMultiSample{ this: CDRInBase => @@ -133,8 +91,6 @@ trait CDRInMultiSample{ this: CDRInBase => //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 - // val diff = Wire(UInt( (log2Ceil(clkNum)).W )) - // diff := arbLock - j.U when( ~isLock ){ for( i <- 3 until 19 ){ val j = 19 - i - 1 @@ -156,7 +112,9 @@ trait CDRInMultiSample{ this: CDRInBase => } } - when( ~isLock ){ + when( io.flush ){ + isLock := false.B + } .elsewhen( ~isLock ){ for( i <- 3 until 19 ){ val j = 19 - i - 1 when( flitReg(j) ^ flitReg(j+1) ){ @@ -199,23 +157,34 @@ trait CDRInAxis{ this: CDRInBase => val bitCnt = Reg(UInt(4.W)) val byteCnt = RegInit(0.U((12+1).W)) - val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) + val checkSFD = RegInit( 0.U(20.W) ) + + when( io.flush ){ + checkSFD := 0.U + } .otherwise{ + checkSFD := Cat( checkSFD(18,0), syncSerDat ) + } val shiftData = Dualb4b5Decoder(checkSFD(9,0)) val payloadLen = RegInit(0.U(12.W)) - when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ + + when( io.flush ){ + payloadLen := 0.U + } .elsewhen( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ payloadLen := Cat( shiftData, 0.U(4.W) ) } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ) } stateNext := - Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE - (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD - )) //crc + Mux( io.flush, STATE_IDLE, + Mux1H(Seq( + (stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE + (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), + (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD + )) //crc + ) @@ -231,7 +200,9 @@ trait CDRInAxis{ this: CDRInBase => } } - when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align + when( io.flush ){ + byteCnt := 0.U + } .elsewhen( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align byteCnt := 0.U } .elsewhen( bitCnt === 9.U ){ when( stateCurr === STATE_HEADER ){ @@ -250,26 +221,29 @@ trait CDRInAxis{ this: CDRInBase => val axis_valid = RegInit(false.B) val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ) val axis_tuser = false.B - val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B ) + val axis_tlast = RegInit( false.B ) + + io.axis.valid := axis_valid io.axis.bits.tdata := axis_tdata io.axis.bits.tuser := axis_tuser io.axis.bits.tlast := axis_tlast - - when( io.axis.fire ){ + when( io.flush ){ + axis_valid := false.B + } .elsewhen( io.axis.fire ){ axis_valid := false.B } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){ axis_valid := true.B } -} + when( io.flush ){ + axis_tlast := false.B + } .otherwise{ + axis_tlast := (stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE) + } -class CDRIn extends CDRInBase -with CDRInAxis -with CDRInOverSample{ - require(false) } class MPCDRIn extends CDRInBase diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index 48d8cf9..1b89b28 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -14,11 +14,13 @@ class CDROutIO extends Bundle{ val axis = Flipped(Decoupled(new AXIS_Bundle(8))) val serDat = Output(Bool()) + val flush = Input(Bool()) + } -class CDROut extends Module{ +class CDROut extends Module with RequireAsyncReset{ val io: CDROutIO = IO(new CDROutIO) def PRE_NUM = 3 //PRE_NUM should >= 3 @@ -39,12 +41,14 @@ class CDROut extends Module{ val shiftData = RegInit(0.U(10.W)) - stateNext := Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), - (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ), - )) - + stateNext := + Mux( io.flush, STATE_IDLE, + Mux1H(Seq( + (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), + (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === (PRE_NUM-1).U) & (bitCnt === 9.U), Mux( io.axis.valid, STATE_PAYLOAD, STATE_IDLE), STATE_PREAMBLE )), + (stateCurr === STATE_PAYLOAD) -> ( Mux( (io.axis.fire & io.axis.bits.tlast) | (~io.axis.valid & io.axis.ready), STATE_IDLE, STATE_PAYLOAD ) ), + )) + ) io.serDat := shiftData.extract(9) io.axis.ready := bitCnt === 9.U & ( @@ -58,8 +62,9 @@ class CDROut extends Module{ } - - when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE + when( io.flush ){ + shiftData := 0.U + } .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE shiftData := ETH_PRE } .otherwise{ when( bitCnt =/= 9.U ){ diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala b/src/main/scala/backBoard/ebus/RoCC2CDR.scala.bk similarity index 100% rename from src/main/scala/backBoard/ebus/RoCC2CDR.scala rename to src/main/scala/backBoard/ebus/RoCC2CDR.scala.bk diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala.bk similarity index 97% rename from src/main/scala/backBoard/ebus/TL2CDR.scala rename to src/main/scala/backBoard/ebus/TL2CDR.scala.bk index 5158fdb..fc40bde 100644 --- a/src/main/scala/backBoard/ebus/TL2CDR.scala +++ b/src/main/scala/backBoard/ebus/TL2CDR.scala.bk @@ -1,456 +1,456 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ - - -class TL2CDR(implicit p: Parameters) extends LazyModule{ - val device = new SimpleDevice("TL_CDR", Nil) - val node = TLManagerNode(Seq(TLSlavePortParameters.v1( - managers = Seq( - TLSlaveParameters.v2( - address = Seq(AddressSet(0x10000000L, 0xffffL)), //64K - name = Some("TL_CDR"), - regionType = RegionType.VOLATILE, - resources = device.reg, - executable = false, - fifoId = Some(0), - supports = TLMasterToSlaveTransferSizes( - get = TransferSizes(1, 32/8), - putFull = TransferSizes(1, 32/8), - putPartial = TransferSizes(1, 32/8), - ), - ) - ), - beatBytes = 32/8))) - - val int_node = IntSourceNode(IntSourcePortSimple(num = 12, resources = device.int)) - - lazy val module: TL2CDRImpl = new TL2CDRImpl(this) -} - - - - - -abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) { - class TLCDRIO extends Bundle{ - val overCLK = Input(Bool()) - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - - val isOnline = Output(Bool()) - val isLast = Input(Bool()) - } - - val io: TLCDRIO = IO(new TLCDRIO) - - val ( int, _ ) = outer.int_node.out(0) - val ( bus, edge ) = outer.node.in.head - - val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } - when(true.B){ - print("Warning!!! New Code has not been reviewed!\n") - } - - CDRIn(0).io.serDat := io.dDatIn - CDRIn(1).io.serDat := io.uDatIn - - CDRIn(0).overCLK := io.overCLK - CDRIn(1).overCLK := io.overCLK - - val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } - - io.dDatOut := CDROut(0).io.serDat - io.uDatOut := CDROut(1).io.serDat - - val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - - val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } - val isTLReadStatus = Wire( Bool() ) - - val txLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } - val rxLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } - -} - - -trait TL2CDRImplTx{ this: TL2CDRImplBase => - - - val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) } - val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) } - - - val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) } - val txLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isTxBusy = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready } - val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) } - val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast } - val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) } - - val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire } - // println("Warning, TxEnd no confident\n") - - - val txCnt = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) } - val txData = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } - - for( i <- 0 until 2 ) { - when( txFifo(i).io.deq.fire ){ //txCnt(i) === 3.U - txData(i) := txFifo(i).io.deq.bits - when( isTxBusy(i) ){ - assert(CDROut(i).io.axis.fire) - } - } .elsewhen( CDROut(i).io.axis.fire ){ - txData(i) := txData(i) << 8 - } - - txFifo(i).io.deq.ready := - isTxFifoRelease(i) & Mux( isTxBusy(i), CDROut(i).io.axis.fire & txCnt(i) === 3.U, true.B ) - - txFifo(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - CDROut(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - - CDROut(i).io.axis.bits.tdata := txData(i).head(8) - CDROut(i).io.axis.bits.tlast := ~txFifo(i).io.deq.valid & txCnt(i) === 3.U - CDROut(i).io.axis.bits.tuser := false.B - CDROut(i).io.axis.valid := isTxBusy(i) - - - when( isTLWriteSoftReset(i) ){ - isTxBusy(i) := false.B - }.elsewhen( txFifo(i).io.deq.fire & ~isTxBusy(i) ){ - isTxBusy(i) := true.B - } .elsewhen( CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast ){ - isTxBusy(i) := false.B - } - - - when( isTLWriteSoftReset(0+i) ){ - txCnt(i) := 0.U - } .elsewhen( CDROut(i).io.axis.fire ){ - txCnt(i) := txCnt(i) + 1.U - } - - - when( isTLWriteTxLen(i) ){ - txLen(i) := bus.a.bits.data - } .elsewhen( CDROut(i).io.axis.fire ){ - txLen(i) := txLen(i) - 1.U - } - - txFifo(i).io.enq.bits := bus.a.bits.data - txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U - - when( isTLWriteSoftReset(0+i) ){ - txLeft(i) := 0.U - } .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){ - txLeft(i) := txLeft(i) - } .elsewhen( txFifo(i).io.enq.fire ){ - txLeft(i) := txLeft(i) + 1.U - } .elsewhen( txFifo(i).io.deq.fire ){ - txLeft(i) := txLeft(i) - 1.U - } - - } - - - -} - - -trait TL2CDRImplRx{ this: TL2CDRImplBase => - - val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid } - val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid } - val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) } - val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire } - val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) } - val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire } - val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) } - val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) } - - for( i <- 0 until 2 ) { - when( isTLWriteSoftReset(2+i) ){ - isAxisEnd(i) := false.B - } .elsewhen( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast ){ - isAxisEnd(i) := true.B - } - - when( isTLWriteSoftReset(2+i) ){ - rxCnt(i) := 0.U - } .elsewhen( CDRIn(i).io.axis.fire ){ - rxCnt(i) := rxCnt(i) + 1.U - rxData(i) := Cat( rxData(i), CDRIn(i).io.axis.bits.tdata ) - } - - when( isTLWriteSoftReset(2+i) ){ - rxLen(i) := 0.U - } .elsewhen( CDRIn(i).io.axis.fire ){ - rxLen(i) := rxLen(i) + 1.U - } - - rxFifo(i).io.enq.valid := CDRIn(i).io.axis.fire & rxCnt(i) === 3.U - rxFifo(i).io.enq.bits := Cat( rxData(i)(23, 0) , CDRIn(i).io.axis.bits.tdata ) - - assert( ~(( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast) & rxCnt(i) =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) - - CDRIn(i).io.axis.ready := true.B - - rxFifo(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - CDRIn(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - - rxFifo(i).io.deq.ready := isTLReadRxFifo(i) - - - when( isTLWriteSoftReset(2+i) ){ - isRxError(i) := false.B - } .elsewhen( rxFifo(i).io.enq.valid & ~rxFifo(i).io.enq.ready ){ - isRxError(i) := true.B - printf(s"Warning, RxFifo$i Overflow!\n") - } - - when( isTLWriteSoftReset(2+i) ){ - rxLeft(i) := 0.U - } .elsewhen( rxFifo(i).io.enq.fire & rxFifo(i).io.deq.fire ){ - rxLeft(i) := rxLeft(i) - } .elsewhen( rxFifo(i).io.enq.fire ){ - rxLeft(i) := rxLeft(i) + 1.U - } .elsewhen( rxFifo(i).io.deq.fire ){ - rxLeft(i) := rxLeft(i) - 1.U - } - } - - - - -} - -trait TL2CDRImplIsLast{ this:TL2CDRImplBase => - io.isOnline := false.B - val isReadIsLast = Wire(Bool()) - -} - -trait TL2CDRImplUserCRC{ this: TL2CDRImplBase => - val isTLWriteTxFifo: Seq[Bool] - val isTLReadRxFifo: Seq[Bool] - - val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - - val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } - val rxCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } - - for( i <- 0 until 2 ) { - txCrc(i).io.enq.valid := isTLWriteTxFifo(i) - txCrc(i).io.enq.bits := bus.a.bits.data - - rxCrc(i).io.enq.valid := isTLReadRxFifo(i) - rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits - - txCrc(i).reset := reset.asBool | isTLWriteSoftReset(0+i) - rxCrc(i).reset := reset.asBool | isTLWriteSoftReset(2+i) - } - - - - -} - -trait TL2CDRImplLimitTimmer{ this: TL2CDRImplBase => - val intRxStart: Seq[Bool] - val isTLWriteSoftReset: Seq[Bool] - val isTxFifoRelease: Seq[Bool] - - val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) } - - val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } - val limitTimerAim = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } - val isLimitTimerTrigger = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val txPairSel = for( i <- 0 until 2 ) yield { RegInit((i.U)(2.W)) } - - for( i <- 0 until 2 ){ - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - limitTimerCnt(i) := 0.U - } .elsewhen( limitTimerCnt(i) =/= limitTimerAim(i) ){ - when( isLimitTimerTrigger(i) ){ - limitTimerCnt(i) := limitTimerCnt(i) + 1.U - } - } - - when( isTLWriteLimitTimerAim(i) ){ - limitTimerAim(i) := bus.a.bits.data - } - - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - isLimitTimerTrigger(i) := false.B - } .elsewhen( intRxStart(i) ){ - isLimitTimerTrigger(i) := true.B - } - - when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ - txPairSel(i) := i.U - } .elsewhen( isTLWriteLimitTxPair(i) ){ - txPairSel(i) := bus.a.bits.data - } - - - isTxFifoRelease(i) := ( 0 until 2).map{ lmt => - ((txPairSel(lmt) =/= i.U) | (limitTimerCnt(lmt) === limitTimerAim(lmt))) - }.reduce(_&_) - - } - -} - - - - - - - - -class TL2CDRImpl(outer: TL2CDR)(implicit p: Parameters) extends TL2CDRImplBase(outer) -with TL2CDRImplTx with TL2CDRImplRx -with TL2CDRImplIsLast -with TL2CDRImplUserCRC -with TL2CDRImplLimitTimmer -{ - - isTLWriteSoftReset(0) := bus.a.fire & bus.a.bits.address(7,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxLen(0) := bus.a.fire & bus.a.bits.address(7,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxFifo(0) := bus.a.fire & bus.a.bits.address(7,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadTxCrc(0) := bus.a.fire & bus.a.bits.address(7,0) === "h0c".U & bus.a.bits.opcode === 4.U - - isTLWriteSoftReset(1) := bus.a.fire & bus.a.bits.address(7,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxLen(1) := bus.a.fire & bus.a.bits.address(7,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteTxFifo(1) := bus.a.fire & bus.a.bits.address(7,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadTxCrc(1) := bus.a.fire & bus.a.bits.address(7,0) === "h1c".U & bus.a.bits.opcode === 4.U - - isTLWriteSoftReset(2) := bus.a.fire & bus.a.bits.address(7,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadRxLen(0) := bus.a.fire & bus.a.bits.address(7,0) === "h24".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxFifo(0) := bus.a.fire & bus.a.bits.address(7,0) === "h28".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxCrc(0) := bus.a.fire & bus.a.bits.address(7,0) === "h2c".U & bus.a.bits.opcode === 4.U - isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(7,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteLimitTxPair(0) := bus.a.fire & bus.a.bits.address(7,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - - isTLWriteSoftReset(3) := bus.a.fire & bus.a.bits.address(7,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadRxLen(1) := bus.a.fire & bus.a.bits.address(7,0) === "h44".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxFifo(1) := bus.a.fire & bus.a.bits.address(7,0) === "h48".U & ( bus.a.bits.opcode === 4.U ) - isTLReadRxCrc(1) := bus.a.fire & bus.a.bits.address(7,0) === "h4c".U & bus.a.bits.opcode === 4.U - isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(7,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteLimitTxPair(1) := bus.a.fire & bus.a.bits.address(7,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - - isTLReadStatus := bus.a.fire & bus.a.bits.address(7,0) === "h58".U & ( bus.a.bits.opcode === 4.U ) - isReadIsLast := bus.a.fire & bus.a.bits.address(7,0) === "h5c".U & ( bus.a.bits.opcode === 4.U ) - - int(0) := intTxEnd(0) - int(1) := intTxEnd(1) - - int(2) := intRxError(0) - int(3) := intRxError(1) - - int(4) := intRxStart(0) - int(5) := intRxStart(1) - - int(6) := intRxEnd(0) - int(7) := intRxEnd(1) - - int(8) := intTxFifoDeq(0) - int(9) := intTxFifoDeq(1) - - int(10) := intRxFifoEnq(0) - int(11) := intRxFifoEnq(1) - - - - - val tlaInfo = Reg(new TLBundleA(edge.bundle)) - val rdata = Reg(UInt(32.W)) - val tlAReady = RegInit(true.B) - val tlDValid = RegInit(false.B) - - val isRead = tlaInfo.opcode === 4.U - - - - - - bus.a.ready := - tlAReady & - MuxCase( true.B, Array( - ( bus.a.bits.address(7,0) === "h08".U ) -> txFifo(0).io.enq.ready, - ( bus.a.bits.address(7,0) === "h18".U ) -> txFifo(1).io.enq.ready, - ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid, - ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid, - )) - - - bus.d.valid := tlDValid - - - - - when( bus.a.fire ) { - tlaInfo := bus.a.bits - } - - when( bus.a.fire ){ - tlAReady := false.B - tlDValid := true.B - } .elsewhen( bus.d.fire ) { - tlAReady := true.B - tlDValid := false.B - } - - when(isRead) { - bus.d.bits := edge.AccessAck(tlaInfo, rdata) - } .otherwise { - bus.d.bits := edge.AccessAck(tlaInfo) - } - - - when( isTLReadStatus ){ - rdata := Cat( txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) ) - } .elsewhen(isTLReadRxLen(0) ){ - rdata := rxLen(0) - } .elsewhen(isTLReadRxLen(1) ){ - rdata := rxLen(1) - } .elsewhen(isTLReadRxFifo(0) ){ - rdata := rxFifo(0).io.deq.bits - } .elsewhen(isTLReadRxFifo(1) ){ - rdata := rxFifo(1).io.deq.bits - } .elsewhen(isReadIsLast){ - rdata := io.isLast - } .elsewhen(isTLReadTxCrc(0)){ - rdata := txCrc(0).io.crc - } .elsewhen(isTLReadTxCrc(1)){ - rdata := txCrc(1).io.crc - } .elsewhen(isTLReadRxCrc(0)){ - rdata := rxCrc(0).io.crc - } .elsewhen(isTLReadRxCrc(1)){ - rdata := rxCrc(1).io.crc - } - -} - - +package BACK + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ + + +class TL2CDR(implicit p: Parameters) extends LazyModule{ + val device = new SimpleDevice("TL_CDR", Nil) + val node = TLManagerNode(Seq(TLSlavePortParameters.v1( + managers = Seq( + TLSlaveParameters.v2( + address = Seq(AddressSet(0x10000000L, 0xffffL)), //64K + name = Some("TL_CDR"), + regionType = RegionType.VOLATILE, + resources = device.reg, + executable = false, + fifoId = Some(0), + supports = TLMasterToSlaveTransferSizes( + get = TransferSizes(1, 32/8), + putFull = TransferSizes(1, 32/8), + putPartial = TransferSizes(1, 32/8), + ), + ) + ), + beatBytes = 32/8))) + + val int_node = IntSourceNode(IntSourcePortSimple(num = 12, resources = device.int)) + + lazy val module: TL2CDRImpl = new TL2CDRImpl(this) +} + + + + + +abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) { + class TLCDRIO extends Bundle{ + val overCLK = Input(Bool()) + val dDatIn = Input(Bool()) + val dDatOut = Output(Bool()) + val uDatIn = Input(Bool()) + val uDatOut = Output(Bool()) + + val isOnline = Output(Bool()) + val isLast = Input(Bool()) + } + + val io: TLCDRIO = IO(new TLCDRIO) + + val ( int, _ ) = outer.int_node.out(0) + val ( bus, edge ) = outer.node.in.head + + val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } + when(true.B){ + print("Warning!!! New Code has not been reviewed!\n") + } + + CDRIn(0).io.serDat := io.dDatIn + CDRIn(1).io.serDat := io.uDatIn + + CDRIn(0).overCLK := io.overCLK + CDRIn(1).overCLK := io.overCLK + + val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } + + io.dDatOut := CDROut(0).io.serDat + io.uDatOut := CDROut(1).io.serDat + + val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } + val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } + + val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } + val isTLReadStatus = Wire( Bool() ) + + val txLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } + val rxLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) } + +} + + +trait TL2CDRImplTx{ this: TL2CDRImplBase => + + + val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) } + val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) } + + + val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) } + val txLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } + val isTxBusy = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready } + val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) } + val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast } + val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) } + + val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire } + // println("Warning, TxEnd no confident\n") + + + val txCnt = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) } + val txData = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) } + + for( i <- 0 until 2 ) { + when( txFifo(i).io.deq.fire ){ //txCnt(i) === 3.U + txData(i) := txFifo(i).io.deq.bits + when( isTxBusy(i) ){ + assert(CDROut(i).io.axis.fire) + } + } .elsewhen( CDROut(i).io.axis.fire ){ + txData(i) := txData(i) << 8 + } + + txFifo(i).io.deq.ready := + isTxFifoRelease(i) & Mux( isTxBusy(i), CDROut(i).io.axis.fire & txCnt(i) === 3.U, true.B ) + + txFifo(i).reset := reset.asBool | isTLWriteSoftReset(0+i) + CDROut(i).reset := reset.asBool | isTLWriteSoftReset(0+i) + + CDROut(i).io.axis.bits.tdata := txData(i).head(8) + CDROut(i).io.axis.bits.tlast := ~txFifo(i).io.deq.valid & txCnt(i) === 3.U + CDROut(i).io.axis.bits.tuser := false.B + CDROut(i).io.axis.valid := isTxBusy(i) + + + when( isTLWriteSoftReset(i) ){ + isTxBusy(i) := false.B + }.elsewhen( txFifo(i).io.deq.fire & ~isTxBusy(i) ){ + isTxBusy(i) := true.B + } .elsewhen( CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast ){ + isTxBusy(i) := false.B + } + + + when( isTLWriteSoftReset(0+i) ){ + txCnt(i) := 0.U + } .elsewhen( CDROut(i).io.axis.fire ){ + txCnt(i) := txCnt(i) + 1.U + } + + + when( isTLWriteTxLen(i) ){ + txLen(i) := bus.a.bits.data + } .elsewhen( CDROut(i).io.axis.fire ){ + txLen(i) := txLen(i) - 1.U + } + + txFifo(i).io.enq.bits := bus.a.bits.data + txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U + + when( isTLWriteSoftReset(0+i) ){ + txLeft(i) := 0.U + } .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){ + txLeft(i) := txLeft(i) + } .elsewhen( txFifo(i).io.enq.fire ){ + txLeft(i) := txLeft(i) + 1.U + } .elsewhen( txFifo(i).io.deq.fire ){ + txLeft(i) := txLeft(i) - 1.U + } + + } + + + +} + + +trait TL2CDRImplRx{ this: TL2CDRImplBase => + + val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) } + + val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } + val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid } + val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid } + val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) } + val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire } + val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) } + val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire } + val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) } + val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) } + + for( i <- 0 until 2 ) { + when( isTLWriteSoftReset(2+i) ){ + isAxisEnd(i) := false.B + } .elsewhen( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast ){ + isAxisEnd(i) := true.B + } + + when( isTLWriteSoftReset(2+i) ){ + rxCnt(i) := 0.U + } .elsewhen( CDRIn(i).io.axis.fire ){ + rxCnt(i) := rxCnt(i) + 1.U + rxData(i) := Cat( rxData(i), CDRIn(i).io.axis.bits.tdata ) + } + + when( isTLWriteSoftReset(2+i) ){ + rxLen(i) := 0.U + } .elsewhen( CDRIn(i).io.axis.fire ){ + rxLen(i) := rxLen(i) + 1.U + } + + rxFifo(i).io.enq.valid := CDRIn(i).io.axis.fire & rxCnt(i) === 3.U + rxFifo(i).io.enq.bits := Cat( rxData(i)(23, 0) , CDRIn(i).io.axis.bits.tdata ) + + assert( ~(( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast) & rxCnt(i) =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) + + CDRIn(i).io.axis.ready := true.B + + rxFifo(i).reset := reset.asBool | isTLWriteSoftReset(2+i) + CDRIn(i).reset := reset.asBool | isTLWriteSoftReset(2+i) + + rxFifo(i).io.deq.ready := isTLReadRxFifo(i) + + + when( isTLWriteSoftReset(2+i) ){ + isRxError(i) := false.B + } .elsewhen( rxFifo(i).io.enq.valid & ~rxFifo(i).io.enq.ready ){ + isRxError(i) := true.B + printf(s"Warning, RxFifo$i Overflow!\n") + } + + when( isTLWriteSoftReset(2+i) ){ + rxLeft(i) := 0.U + } .elsewhen( rxFifo(i).io.enq.fire & rxFifo(i).io.deq.fire ){ + rxLeft(i) := rxLeft(i) + } .elsewhen( rxFifo(i).io.enq.fire ){ + rxLeft(i) := rxLeft(i) + 1.U + } .elsewhen( rxFifo(i).io.deq.fire ){ + rxLeft(i) := rxLeft(i) - 1.U + } + } + + + + +} + +trait TL2CDRImplIsLast{ this:TL2CDRImplBase => + io.isOnline := false.B + val isReadIsLast = Wire(Bool()) + +} + +trait TL2CDRImplUserCRC{ this: TL2CDRImplBase => + val isTLWriteTxFifo: Seq[Bool] + val isTLReadRxFifo: Seq[Bool] + + val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } + + + val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } + val rxCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } + + for( i <- 0 until 2 ) { + txCrc(i).io.enq.valid := isTLWriteTxFifo(i) + txCrc(i).io.enq.bits := bus.a.bits.data + + rxCrc(i).io.enq.valid := isTLReadRxFifo(i) + rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits + + txCrc(i).reset := reset.asBool | isTLWriteSoftReset(0+i) + rxCrc(i).reset := reset.asBool | isTLWriteSoftReset(2+i) + } + + + + +} + +trait TL2CDRImplLimitTimmer{ this: TL2CDRImplBase => + val intRxStart: Seq[Bool] + val isTLWriteSoftReset: Seq[Bool] + val isTxFifoRelease: Seq[Bool] + + val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) } + + val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } + val limitTimerAim = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } + val isLimitTimerTrigger = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val txPairSel = for( i <- 0 until 2 ) yield { RegInit((i.U)(2.W)) } + + for( i <- 0 until 2 ){ + when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ + limitTimerCnt(i) := 0.U + } .elsewhen( limitTimerCnt(i) =/= limitTimerAim(i) ){ + when( isLimitTimerTrigger(i) ){ + limitTimerCnt(i) := limitTimerCnt(i) + 1.U + } + } + + when( isTLWriteLimitTimerAim(i) ){ + limitTimerAim(i) := bus.a.bits.data + } + + when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ + isLimitTimerTrigger(i) := false.B + } .elsewhen( intRxStart(i) ){ + isLimitTimerTrigger(i) := true.B + } + + when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ + txPairSel(i) := i.U + } .elsewhen( isTLWriteLimitTxPair(i) ){ + txPairSel(i) := bus.a.bits.data + } + + + isTxFifoRelease(i) := ( 0 until 2).map{ lmt => + ((txPairSel(lmt) =/= i.U) | (limitTimerCnt(lmt) === limitTimerAim(lmt))) + }.reduce(_&_) + + } + +} + + + + + + + + +class TL2CDRImpl(outer: TL2CDR)(implicit p: Parameters) extends TL2CDRImplBase(outer) +with TL2CDRImplTx with TL2CDRImplRx +with TL2CDRImplIsLast +with TL2CDRImplUserCRC +with TL2CDRImplLimitTimmer +{ + + isTLWriteSoftReset(0) := bus.a.fire & bus.a.bits.address(7,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxLen(0) := bus.a.fire & bus.a.bits.address(7,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxFifo(0) := bus.a.fire & bus.a.bits.address(7,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadTxCrc(0) := bus.a.fire & bus.a.bits.address(7,0) === "h0c".U & bus.a.bits.opcode === 4.U + + isTLWriteSoftReset(1) := bus.a.fire & bus.a.bits.address(7,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxLen(1) := bus.a.fire & bus.a.bits.address(7,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxFifo(1) := bus.a.fire & bus.a.bits.address(7,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadTxCrc(1) := bus.a.fire & bus.a.bits.address(7,0) === "h1c".U & bus.a.bits.opcode === 4.U + + isTLWriteSoftReset(2) := bus.a.fire & bus.a.bits.address(7,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadRxLen(0) := bus.a.fire & bus.a.bits.address(7,0) === "h24".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxFifo(0) := bus.a.fire & bus.a.bits.address(7,0) === "h28".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxCrc(0) := bus.a.fire & bus.a.bits.address(7,0) === "h2c".U & bus.a.bits.opcode === 4.U + isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(7,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteLimitTxPair(0) := bus.a.fire & bus.a.bits.address(7,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + + isTLWriteSoftReset(3) := bus.a.fire & bus.a.bits.address(7,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadRxLen(1) := bus.a.fire & bus.a.bits.address(7,0) === "h44".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxFifo(1) := bus.a.fire & bus.a.bits.address(7,0) === "h48".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxCrc(1) := bus.a.fire & bus.a.bits.address(7,0) === "h4c".U & bus.a.bits.opcode === 4.U + isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(7,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteLimitTxPair(1) := bus.a.fire & bus.a.bits.address(7,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + + isTLReadStatus := bus.a.fire & bus.a.bits.address(7,0) === "h58".U & ( bus.a.bits.opcode === 4.U ) + isReadIsLast := bus.a.fire & bus.a.bits.address(7,0) === "h5c".U & ( bus.a.bits.opcode === 4.U ) + + int(0) := intTxEnd(0) + int(1) := intTxEnd(1) + + int(2) := intRxError(0) + int(3) := intRxError(1) + + int(4) := intRxStart(0) + int(5) := intRxStart(1) + + int(6) := intRxEnd(0) + int(7) := intRxEnd(1) + + int(8) := intTxFifoDeq(0) + int(9) := intTxFifoDeq(1) + + int(10) := intRxFifoEnq(0) + int(11) := intRxFifoEnq(1) + + + + + val tlaInfo = Reg(new TLBundleA(edge.bundle)) + val rdata = Reg(UInt(32.W)) + val tlAReady = RegInit(true.B) + val tlDValid = RegInit(false.B) + + val isRead = tlaInfo.opcode === 4.U + + + + + + bus.a.ready := + tlAReady & + MuxCase( true.B, Array( + ( bus.a.bits.address(7,0) === "h08".U ) -> txFifo(0).io.enq.ready, + ( bus.a.bits.address(7,0) === "h18".U ) -> txFifo(1).io.enq.ready, + ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid, + ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid, + )) + + + bus.d.valid := tlDValid + + + + + when( bus.a.fire ) { + tlaInfo := bus.a.bits + } + + when( bus.a.fire ){ + tlAReady := false.B + tlDValid := true.B + } .elsewhen( bus.d.fire ) { + tlAReady := true.B + tlDValid := false.B + } + + when(isRead) { + bus.d.bits := edge.AccessAck(tlaInfo, rdata) + } .otherwise { + bus.d.bits := edge.AccessAck(tlaInfo) + } + + + when( isTLReadStatus ){ + rdata := Cat( txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) ) + } .elsewhen(isTLReadRxLen(0) ){ + rdata := rxLen(0) + } .elsewhen(isTLReadRxLen(1) ){ + rdata := rxLen(1) + } .elsewhen(isTLReadRxFifo(0) ){ + rdata := rxFifo(0).io.deq.bits + } .elsewhen(isTLReadRxFifo(1) ){ + rdata := rxFifo(1).io.deq.bits + } .elsewhen(isReadIsLast){ + rdata := io.isLast + } .elsewhen(isTLReadTxCrc(0)){ + rdata := txCrc(0).io.crc + } .elsewhen(isTLReadTxCrc(1)){ + rdata := txCrc(1).io.crc + } .elsewhen(isTLReadRxCrc(0)){ + rdata := rxCrc(0).io.crc + } .elsewhen(isTLReadRxCrc(1)){ + rdata := rxCrc(1).io.crc + } + +} + + diff --git a/src/main/scala/backBoard/ebus/crc32.scala b/src/main/scala/backBoard/ebus/crc32.scala index 7c51fea..a131189 100644 --- a/src/main/scala/backBoard/ebus/crc32.scala +++ b/src/main/scala/backBoard/ebus/crc32.scala @@ -86,12 +86,13 @@ import chisel3.util._ //----------------------------------------------------------------------------- -class crc32_8() extends Module{ +class crc32_8() extends Module with RequireAsyncReset{ class crc32IO_Bundle extends Bundle{ val isEnable = Input(Bool()) val dataIn = Input(UInt(8.W)) val crc = Output(UInt(32.W)) + val flush = Input(Bool()) } val io = IO( new crc32IO_Bundle ) @@ -99,7 +100,16 @@ class crc32_8() extends Module{ // val LFSR_POLY = "h4c11db7".U val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool()) - val lfsr_q = for( i <- 0 until 32 ) yield RegEnable( lfsr_c(i), true.B, io.isEnable ) + val lfsr_q = for( i <- 0 until 32 ) yield RegInit( true.B ) + + for( i <- 0 until 32 ){ + when( io.flush ){ + lfsr_q(i) := true.B + } .elsewhen( io.isEnable ){ + lfsr_q(i) := lfsr_c(i) + } + } + io.crc := Cat( lfsr_q ) val dataIn = Wire(UInt(8.W)) @@ -142,67 +152,3 @@ class crc32_8() extends Module{ } - - -class crc32_32() extends Module{ - val io = IO(new Bundle{ - val enq = Flipped(Valid(UInt(32.W))) - val crc = Output(UInt(32.W)) - }) - - - - //----------------------------------------------------------------------------- - // Copyright (C) 2009 OutputLogic.com - // This source file may be used and distributed without restriction - // provided that this copyright statement is not removed from the file - // and that any derivative work contains the original copyright notice - // and the associated disclaimer. - // - // THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS - // OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - // WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - //----------------------------------------------------------------------------- - // CRC module for data(31:0) , crc(31:0)=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32; - //----------------------------------------------------------------------------- - - - val lfsr_c = Wire(Vec(32, UInt(1.W))) - val lfsr_q = RegEnable( Cat(lfsr_c.reverse), "hffffffff".U(32.W), io.enq.valid) - - io.crc := lfsr_q - - lfsr_c( 0) := lfsr_q(0) ^ lfsr_q(6) ^ lfsr_q( 9) ^ lfsr_q(10) ^ lfsr_q(12) ^ lfsr_q(16) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(6) ^ io.enq.bits(9) ^ io.enq.bits(10) ^ io.enq.bits(12) ^ io.enq.bits(16) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(28) ^ io.enq.bits(29) ^ io.enq.bits(30) ^ io.enq.bits(31); - lfsr_c( 1) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 6) ^ lfsr_q( 7) ^ lfsr_q( 9) ^ lfsr_q(11) ^ lfsr_q(12) ^ lfsr_q(13) ^ lfsr_q(16) ^ lfsr_q(17) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(9) ^ io.enq.bits(11) ^ io.enq.bits(12) ^ io.enq.bits(13) ^ io.enq.bits(16) ^ io.enq.bits(17) ^ io.enq.bits(24) ^ io.enq.bits(27) ^ io.enq.bits(28); - lfsr_c( 2) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 2) ^ lfsr_q( 6) ^ lfsr_q( 7) ^ lfsr_q( 8) ^ lfsr_q( 9) ^ lfsr_q(13) ^ lfsr_q(14) ^ lfsr_q(16) ^ lfsr_q(17) ^ lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(9) ^ io.enq.bits(13) ^ io.enq.bits(14) ^ io.enq.bits(16) ^ io.enq.bits(17) ^ io.enq.bits(18) ^ io.enq.bits(24) ^ io.enq.bits(26) ^ io.enq.bits(30) ^ io.enq.bits(31); - lfsr_c( 3) := lfsr_q(1) ^ lfsr_q(2) ^ lfsr_q( 3) ^ lfsr_q( 7) ^ lfsr_q( 8) ^ lfsr_q( 9) ^ lfsr_q(10) ^ lfsr_q(14) ^ lfsr_q(15) ^ lfsr_q(17) ^ lfsr_q(18) ^ lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(9) ^ io.enq.bits(10) ^ io.enq.bits(14) ^ io.enq.bits(15) ^ io.enq.bits(17) ^ io.enq.bits(18) ^ io.enq.bits(19) ^ io.enq.bits(25) ^ io.enq.bits(27) ^ io.enq.bits(31); - lfsr_c( 4) := lfsr_q(0) ^ lfsr_q(2) ^ lfsr_q( 3) ^ lfsr_q( 4) ^ lfsr_q( 6) ^ lfsr_q( 8) ^ lfsr_q(11) ^ lfsr_q(12) ^ lfsr_q(15) ^ lfsr_q(18) ^ lfsr_q(19) ^ lfsr_q(20) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(6) ^ io.enq.bits(8) ^ io.enq.bits(11) ^ io.enq.bits(12) ^ io.enq.bits(15) ^ io.enq.bits(18) ^ io.enq.bits(19) ^ io.enq.bits(20) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(29) ^ io.enq.bits(30) ^ io.enq.bits(31); - lfsr_c( 5) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 3) ^ lfsr_q( 4) ^ lfsr_q( 5) ^ lfsr_q( 6) ^ lfsr_q( 7) ^ lfsr_q(10) ^ lfsr_q(13) ^ lfsr_q(19) ^ lfsr_q(20) ^ lfsr_q(21) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(10) ^ io.enq.bits(13) ^ io.enq.bits(19) ^ io.enq.bits(20) ^ io.enq.bits(21) ^ io.enq.bits(24) ^ io.enq.bits(28) ^ io.enq.bits(29); - lfsr_c( 6) := lfsr_q(1) ^ lfsr_q(2) ^ lfsr_q( 4) ^ lfsr_q( 5) ^ lfsr_q( 6) ^ lfsr_q( 7) ^ lfsr_q( 8) ^ lfsr_q(11) ^ lfsr_q(14) ^ lfsr_q(20) ^ lfsr_q(21) ^ lfsr_q(22) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(11) ^ io.enq.bits(14) ^ io.enq.bits(20) ^ io.enq.bits(21) ^ io.enq.bits(22) ^ io.enq.bits(25) ^ io.enq.bits(29) ^ io.enq.bits(30); - lfsr_c( 7) := lfsr_q(0) ^ lfsr_q(2) ^ lfsr_q( 3) ^ lfsr_q( 5) ^ lfsr_q( 7) ^ lfsr_q( 8) ^ lfsr_q(10) ^ lfsr_q(15) ^ lfsr_q(16) ^ lfsr_q(21) ^ lfsr_q(22) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.enq.bits(0) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(5) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(10) ^ io.enq.bits(15) ^ io.enq.bits(16) ^ io.enq.bits(21) ^ io.enq.bits(22) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(28) ^ io.enq.bits(29); - lfsr_c( 8) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 3) ^ lfsr_q( 4) ^ lfsr_q( 8) ^ lfsr_q(10) ^ lfsr_q(11) ^ lfsr_q(12) ^ lfsr_q(17) ^ lfsr_q(22) ^ lfsr_q(23) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(8) ^ io.enq.bits(10) ^ io.enq.bits(11) ^ io.enq.bits(12) ^ io.enq.bits(17) ^ io.enq.bits(22) ^ io.enq.bits(23) ^ io.enq.bits(28) ^ io.enq.bits(31); - lfsr_c( 9) := lfsr_q(1) ^ lfsr_q(2) ^ lfsr_q( 4) ^ lfsr_q( 5) ^ lfsr_q( 9) ^ lfsr_q(11) ^ lfsr_q(12) ^ lfsr_q(13) ^ lfsr_q(18) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(29) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(9) ^ io.enq.bits(11) ^ io.enq.bits(12) ^ io.enq.bits(13) ^ io.enq.bits(18) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(29); - lfsr_c(10) := lfsr_q(0) ^ lfsr_q(2) ^ lfsr_q( 3) ^ lfsr_q( 5) ^ lfsr_q( 9) ^ lfsr_q(13) ^ lfsr_q(14) ^ lfsr_q(16) ^ lfsr_q(19) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(5) ^ io.enq.bits(9) ^ io.enq.bits(13) ^ io.enq.bits(14) ^ io.enq.bits(16) ^ io.enq.bits(19) ^ io.enq.bits(26) ^ io.enq.bits(28) ^ io.enq.bits(29) ^ io.enq.bits(31); - lfsr_c(11) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 3) ^ lfsr_q( 4) ^ lfsr_q( 9) ^ lfsr_q(12) ^ lfsr_q(14) ^ lfsr_q(15) ^ lfsr_q(16) ^ lfsr_q(17) ^ lfsr_q(20) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(9) ^ io.enq.bits(12) ^ io.enq.bits(14) ^ io.enq.bits(15) ^ io.enq.bits(16) ^ io.enq.bits(17) ^ io.enq.bits(20) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(28) ^ io.enq.bits(31); - lfsr_c(12) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 2) ^ lfsr_q( 4) ^ lfsr_q( 5) ^ lfsr_q( 6) ^ lfsr_q( 9) ^ lfsr_q(12) ^ lfsr_q(13) ^ lfsr_q(15) ^ lfsr_q(17) ^ lfsr_q(18) ^ lfsr_q(21) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(6) ^ io.enq.bits(9) ^ io.enq.bits(12) ^ io.enq.bits(13) ^ io.enq.bits(15) ^ io.enq.bits(17) ^ io.enq.bits(18) ^ io.enq.bits(21) ^ io.enq.bits(24) ^ io.enq.bits(27) ^ io.enq.bits(30) ^ io.enq.bits(31); - lfsr_c(13) := lfsr_q(1) ^ lfsr_q(2) ^ lfsr_q( 3) ^ lfsr_q( 5) ^ lfsr_q( 6) ^ lfsr_q( 7) ^ lfsr_q(10) ^ lfsr_q(13) ^ lfsr_q(14) ^ lfsr_q(16) ^ lfsr_q(18) ^ lfsr_q(19) ^ lfsr_q(22) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(5) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(10) ^ io.enq.bits(13) ^ io.enq.bits(14) ^ io.enq.bits(16) ^ io.enq.bits(18) ^ io.enq.bits(19) ^ io.enq.bits(22) ^ io.enq.bits(25) ^ io.enq.bits(28) ^ io.enq.bits(31); - lfsr_c(14) := lfsr_q(2) ^ lfsr_q(3) ^ lfsr_q( 4) ^ lfsr_q( 6) ^ lfsr_q( 7) ^ lfsr_q( 8) ^ lfsr_q(11) ^ lfsr_q(14) ^ lfsr_q(15) ^ lfsr_q(17) ^ lfsr_q(19) ^ lfsr_q(20) ^ lfsr_q(23) ^ lfsr_q(26) ^ lfsr_q(29) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(11) ^ io.enq.bits(14) ^ io.enq.bits(15) ^ io.enq.bits(17) ^ io.enq.bits(19) ^ io.enq.bits(20) ^ io.enq.bits(23) ^ io.enq.bits(26) ^ io.enq.bits(29); - lfsr_c(15) := lfsr_q(3) ^ lfsr_q(4) ^ lfsr_q( 5) ^ lfsr_q( 7) ^ lfsr_q( 8) ^ lfsr_q( 9) ^ lfsr_q(12) ^ lfsr_q(15) ^ lfsr_q(16) ^ lfsr_q(18) ^ lfsr_q(20) ^ lfsr_q(21) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(30) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(9) ^ io.enq.bits(12) ^ io.enq.bits(15) ^ io.enq.bits(16) ^ io.enq.bits(18) ^ io.enq.bits(20) ^ io.enq.bits(21) ^ io.enq.bits(24) ^ io.enq.bits(27) ^ io.enq.bits(30); - lfsr_c(16) := lfsr_q(0) ^ lfsr_q(4) ^ lfsr_q( 5) ^ lfsr_q( 8) ^ lfsr_q(12) ^ lfsr_q(13) ^ lfsr_q(17) ^ lfsr_q(19) ^ lfsr_q(21) ^ lfsr_q(22) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.enq.bits(0) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(8) ^ io.enq.bits(12) ^ io.enq.bits(13) ^ io.enq.bits(17) ^ io.enq.bits(19) ^ io.enq.bits(21) ^ io.enq.bits(22) ^ io.enq.bits(24) ^ io.enq.bits(26) ^ io.enq.bits(29) ^ io.enq.bits(30); - lfsr_c(17) := lfsr_q(1) ^ lfsr_q(5) ^ lfsr_q( 6) ^ lfsr_q( 9) ^ lfsr_q(13) ^ lfsr_q(14) ^ lfsr_q(18) ^ lfsr_q(20) ^ lfsr_q(22) ^ lfsr_q(23) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.enq.bits(1) ^ io.enq.bits(5) ^ io.enq.bits(6) ^ io.enq.bits(9) ^ io.enq.bits(13) ^ io.enq.bits(14) ^ io.enq.bits(18) ^ io.enq.bits(20) ^ io.enq.bits(22) ^ io.enq.bits(23) ^ io.enq.bits(25) ^ io.enq.bits(27) ^ io.enq.bits(30) ^ io.enq.bits(31); - lfsr_c(18) := lfsr_q(2) ^ lfsr_q(6) ^ lfsr_q( 7) ^ lfsr_q(10) ^ lfsr_q(14) ^ lfsr_q(15) ^ lfsr_q(19) ^ lfsr_q(21) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.enq.bits(2) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(10) ^ io.enq.bits(14) ^ io.enq.bits(15) ^ io.enq.bits(19) ^ io.enq.bits(21) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(26) ^ io.enq.bits(28) ^ io.enq.bits(31); - lfsr_c(19) := lfsr_q(3) ^ lfsr_q(7) ^ lfsr_q( 8) ^ lfsr_q(11) ^ lfsr_q(15) ^ lfsr_q(16) ^ lfsr_q(20) ^ lfsr_q(22) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(29) ^ io.enq.bits(3) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(11) ^ io.enq.bits(15) ^ io.enq.bits(16) ^ io.enq.bits(20) ^ io.enq.bits(22) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(27) ^ io.enq.bits(29); - lfsr_c(20) := lfsr_q(4) ^ lfsr_q(8) ^ lfsr_q( 9) ^ lfsr_q(12) ^ lfsr_q(16) ^ lfsr_q(17) ^ lfsr_q(21) ^ lfsr_q(23) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.enq.bits(4) ^ io.enq.bits(8) ^ io.enq.bits(9) ^ io.enq.bits(12) ^ io.enq.bits(16) ^ io.enq.bits(17) ^ io.enq.bits(21) ^ io.enq.bits(23) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(28) ^ io.enq.bits(30); - lfsr_c(21) := lfsr_q(5) ^ lfsr_q(9) ^ lfsr_q(10) ^ lfsr_q(13) ^ lfsr_q(17) ^ lfsr_q(18) ^ lfsr_q(22) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.enq.bits(5) ^ io.enq.bits(9) ^ io.enq.bits(10) ^ io.enq.bits(13) ^ io.enq.bits(17) ^ io.enq.bits(18) ^ io.enq.bits(22) ^ io.enq.bits(24) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(29) ^ io.enq.bits(31); - lfsr_c(22) := lfsr_q(0) ^ lfsr_q(9) ^ lfsr_q(11) ^ lfsr_q(12) ^ lfsr_q(14) ^ lfsr_q(16) ^ lfsr_q(18) ^ lfsr_q(19) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(9) ^ io.enq.bits(11) ^ io.enq.bits(12) ^ io.enq.bits(14) ^ io.enq.bits(16) ^ io.enq.bits(18) ^ io.enq.bits(19) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(29) ^ io.enq.bits(31); - lfsr_c(23) := lfsr_q(0) ^ lfsr_q(1) ^ lfsr_q( 6) ^ lfsr_q( 9) ^ lfsr_q(13) ^ lfsr_q(15) ^ lfsr_q(16) ^ lfsr_q(17) ^ lfsr_q(19) ^ lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(1) ^ io.enq.bits(6) ^ io.enq.bits(9) ^ io.enq.bits(13) ^ io.enq.bits(15) ^ io.enq.bits(16) ^ io.enq.bits(17) ^ io.enq.bits(19) ^ io.enq.bits(20) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(29) ^ io.enq.bits(31); - lfsr_c(24) := lfsr_q(1) ^ lfsr_q(2) ^ lfsr_q( 7) ^ lfsr_q(10) ^ lfsr_q(14) ^ lfsr_q(16) ^ lfsr_q(17) ^ lfsr_q(18) ^ lfsr_q(20) ^ lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.enq.bits(1) ^ io.enq.bits(2) ^ io.enq.bits(7) ^ io.enq.bits(10) ^ io.enq.bits(14) ^ io.enq.bits(16) ^ io.enq.bits(17) ^ io.enq.bits(18) ^ io.enq.bits(20) ^ io.enq.bits(21) ^ io.enq.bits(27) ^ io.enq.bits(28) ^ io.enq.bits(30); - lfsr_c(25) := lfsr_q(2) ^ lfsr_q(3) ^ lfsr_q( 8) ^ lfsr_q(11) ^ lfsr_q(15) ^ lfsr_q(17) ^ lfsr_q(18) ^ lfsr_q(19) ^ lfsr_q(21) ^ lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.enq.bits(2) ^ io.enq.bits(3) ^ io.enq.bits(8) ^ io.enq.bits(11) ^ io.enq.bits(15) ^ io.enq.bits(17) ^ io.enq.bits(18) ^ io.enq.bits(19) ^ io.enq.bits(21) ^ io.enq.bits(22) ^ io.enq.bits(28) ^ io.enq.bits(29) ^ io.enq.bits(31); - lfsr_c(26) := lfsr_q(0) ^ lfsr_q(3) ^ lfsr_q( 4) ^ lfsr_q( 6) ^ lfsr_q(10) ^ lfsr_q(18) ^ lfsr_q(19) ^ lfsr_q(20) ^ lfsr_q(22) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.enq.bits(0) ^ io.enq.bits(3) ^ io.enq.bits(4) ^ io.enq.bits(6) ^ io.enq.bits(10) ^ io.enq.bits(18) ^ io.enq.bits(19) ^ io.enq.bits(20) ^ io.enq.bits(22) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(28) ^ io.enq.bits(31); - lfsr_c(27) := lfsr_q(1) ^ lfsr_q(4) ^ lfsr_q( 5) ^ lfsr_q( 7) ^ lfsr_q(11) ^ lfsr_q(19) ^ lfsr_q(20) ^ lfsr_q(21) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ io.enq.bits(1) ^ io.enq.bits(4) ^ io.enq.bits(5) ^ io.enq.bits(7) ^ io.enq.bits(11) ^ io.enq.bits(19) ^ io.enq.bits(20) ^ io.enq.bits(21) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(29); - lfsr_c(28) := lfsr_q(2) ^ lfsr_q(5) ^ lfsr_q( 6) ^ lfsr_q( 8) ^ lfsr_q(12) ^ lfsr_q(20) ^ lfsr_q(21) ^ lfsr_q(22) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.enq.bits(2) ^ io.enq.bits(5) ^ io.enq.bits(6) ^ io.enq.bits(8) ^ io.enq.bits(12) ^ io.enq.bits(20) ^ io.enq.bits(21) ^ io.enq.bits(22) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(28) ^ io.enq.bits(30); - lfsr_c(29) := lfsr_q(3) ^ lfsr_q(6) ^ lfsr_q( 7) ^ lfsr_q( 9) ^ lfsr_q(13) ^ lfsr_q(21) ^ lfsr_q(22) ^ lfsr_q(23) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.enq.bits(3) ^ io.enq.bits(6) ^ io.enq.bits(7) ^ io.enq.bits(9) ^ io.enq.bits(13) ^ io.enq.bits(21) ^ io.enq.bits(22) ^ io.enq.bits(23) ^ io.enq.bits(25) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(28) ^ io.enq.bits(29) ^ io.enq.bits(31); - lfsr_c(30) := lfsr_q(4) ^ lfsr_q(7) ^ lfsr_q( 8) ^ lfsr_q(10) ^ lfsr_q(14) ^ lfsr_q(22) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.enq.bits(4) ^ io.enq.bits(7) ^ io.enq.bits(8) ^ io.enq.bits(10) ^ io.enq.bits(14) ^ io.enq.bits(22) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(26) ^ io.enq.bits(27) ^ io.enq.bits(28) ^ io.enq.bits(29) ^ io.enq.bits(30); - lfsr_c(31) := lfsr_q(5) ^ lfsr_q(8) ^ lfsr_q( 9) ^ lfsr_q(11) ^ lfsr_q(15) ^ lfsr_q(23) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.enq.bits(5) ^ io.enq.bits(8) ^ io.enq.bits(9) ^ io.enq.bits(11) ^ io.enq.bits(15) ^ io.enq.bits(23) ^ io.enq.bits(24) ^ io.enq.bits(25) ^ io.enq.bits(27) ^ io.enq.bits(28) ^ io.enq.bits(29) ^ io.enq.bits(30) ^ io.enq.bits(31); - -} diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index d64aca5..918ed57 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -213,7 +213,7 @@ class InterfaceIO extends Bundle{ } -abstract class InterfaceBase extends Module{ +abstract class InterfaceBase extends Module with RequireAsyncReset{ val io: InterfaceIO = IO(new InterfaceIO) val oSpi = Module(new SSpiInterface) diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index 7d1be5e..b80ac36 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -27,7 +27,7 @@ class MasterParserIO extends Bundle{ } -abstract class MasterParserBase extends Module{ +abstract class MasterParserBase extends Module with RequireAsyncReset{ val io: MasterParserIO = IO(new MasterParserIO) val txCnt = Reg(UInt(12.W)) @@ -167,11 +167,11 @@ abstract class MasterParserBase extends Module{ txcrc.io.isEnable := io.downOut.fire & txCnt < txLen txcrc.io.dataIn := io.downOut.bits.tdata - txcrc.reset := reset.asBool | reqReady + txcrc.io.flush := reqReady rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen rxcrc.io.dataIn := io.upIn.bits.tdata - rxcrc.reset := reset.asBool | io.rsp.fire + rxcrc.io.flush := io.rsp.fire diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala index d761ee0..15acb50 100644 --- a/src/main/scala/backBoard/shin/SMUnit.scala +++ b/src/main/scala/backBoard/shin/SMUnit.scala @@ -33,9 +33,11 @@ class SMUnitIO(depth: Int) extends Bundle { val sram = Flipped(Vec(depth, new SRAM2kIO)) val cnt = Output(UInt(8.W)) + val flush = Input(Bool()) + } -abstract class SMUnitBase(depth: Int = 4) extends Module { +abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{ val io: SMUnitIO = IO(new SMUnitIO(depth)) @@ -43,18 +45,19 @@ abstract class SMUnitBase(depth: Int = 4) extends Module { val rPtr = RegInit(0.U((log2Ceil(depth)+1).W)) val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth)) - // ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) ) - val isEmpty = ( wPtr === rPtr ) - - when( io.enq & ~isFull ){ + when(io.flush){ + wPtr := 0.U + } .elsewhen( io.enq & ~isFull ){ wPtr := wPtr + 1.U // assert( ~isFull) } - when( io.deq & ~isEmpty ){ + when(io.flush){ + rPtr := 0.U + } .elsewhen( io.deq & ~isEmpty ){ rPtr := rPtr + 1.U // assert( ~isEmpty ) } @@ -87,7 +90,9 @@ abstract class SMUnitBase(depth: Int = 4) extends Module { val cnt = RegInit(0.U((log2Ceil(depth+1)).W)); io.cnt := cnt - when( io.enq & ~isFull ){ + when( io.flush ){ + cnt := 0.U + } .elsewhen( io.enq & ~isFull ){ cnt := cnt + 1.U assert(cnt =/= depth.U) } .elsewhen( io.deq & ~isEmpty ){ diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index d1e9372..4cb6d89 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -49,7 +49,7 @@ class ShinTopIO extends Bundle{ -abstract class ShinTopBase extends Module{ +abstract class ShinTopBase extends Module with RequireAsyncReset{ val io: ShinTopIO = IO(new ShinTopIO) @@ -160,7 +160,7 @@ abstract class ShinTopBase extends Module{ for( i <- 0 until 8 ){ interface.io.smUsedDepth(i) := smUnit(i).io.cnt - smUnit(i).reset := reset.asBool | interface.io.isSMReset(i) + smUnit(i).io.flush := interface.io.isSMReset(i) } @@ -380,10 +380,10 @@ trait ShinTopSlave{ this: ShinTopBase => slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - downCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) - downCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) interface.io.lvds <> slaveParser.io.lvds diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 72510ab..e550798 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -82,7 +82,7 @@ class SlaveParserIO extends Bundle{ val upRecStat = Output(new Stat_IO_Bundle) } -abstract class SlaveParserBase extends Module{ +abstract class SlaveParserBase extends Module with RequireAsyncReset{ val io: SlaveParserIO = IO(new SlaveParserIO) val sReg = io.sReg @@ -991,11 +991,11 @@ with SlaveParserProbe{ io.intHWTrig(0) := downRecParser.io.isError io.intHWTrig(1) := upRecParser.io.isError - downRecParser.reset := reset.asBool | RegNext(downRecParser.io.isError & io.intHWClr(0)) - downSendGen.reset := reset.asBool | RegNext(downRecParser.io.isError & io.intHWClr(0)) + downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0)) + downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0)) - upRecParser.reset := reset.asBool | RegNext(upRecParser.io.isError & io.intHWClr(1)) - upSendGen.reset := reset.asBool | RegNext(upRecParser.io.isError & io.intHWClr(1)) + upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1)) + upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1)) io.downRecStat := downRecParser.io.stat io.upRecStat := upRecParser.io.stat diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index 697eba0..0c9e27c 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -20,10 +20,10 @@ class SlaveRecParserIO extends Bundle{ val stat = Output(new Stat_IO_Bundle) - + val flush = Input(Bool()) } -class SlaveRecParser extends Module{ +class SlaveRecParser extends Module with RequireAsyncReset{ val io: SlaveRecParserIO = IO(new SlaveRecParserIO) val crc = Module(new crc32_8) @@ -53,7 +53,7 @@ class SlaveRecParser extends Module{ crc.io.dataIn := io.rec.bits.tdata - crc.reset := reset.asBool | stateCurr === STATE_IDLE + crc.io.flush := stateCurr === STATE_IDLE | io.flush val crcData = Reg(UInt(32.W)) val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata ) @@ -96,7 +96,9 @@ class SlaveRecParser extends Module{ io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0) - when( io.rec.fire ){ + when( io.flush ){ + lengthCnt := 0.U + } .elsewhen( io.rec.fire ){ when( stateCurr =/= stateNext ){ lengthCnt := 0.U } .otherwise{ @@ -177,36 +179,38 @@ class SlaveRecParser extends Module{ stateNext := - Mux1H(Seq( - //必须使用上升沿触发，以避免前一帧长度超过预期 - ( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ), - ( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, - Mux( lengthCnt === (4-1).U, - MuxCase( STATE_ERROR, Array( - ( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER, - ( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC, + Mux( io.flush, STATE_IDLE, + Mux1H(Seq( + //必须使用上升沿触发，以避免前一帧长度超过预期 + ( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ), + ( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, + Mux( lengthCnt === (4-1).U, + MuxCase( STATE_ERROR, Array( + ( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER, + ( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC, + )), STATE_HEADER )), STATE_HEADER - )), STATE_HEADER + ), + ( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, + Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) + ), STATE_SUBMSG_HEADER), + + ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, + Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA ) + ), STATE_PAYLOAD_DATA), + + ( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, + Mux( lengthCnt === ( (2 - 1).U), + Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER + ),STATE_SUBMSG_TAIL ) + ), STATE_SUBMSG_TAIL), + + ( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast, + Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC ), - ( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, - Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) - ), STATE_SUBMSG_HEADER), - - ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, - Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA ) - ), STATE_PAYLOAD_DATA), - - ( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, - Mux( lengthCnt === ( (2 - 1).U), - Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER - ),STATE_SUBMSG_TAIL ) - ), STATE_SUBMSG_TAIL), - - ( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast, - Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC - ), - ( stateCurr === STATE_ERROR ) -> STATE_ERROR, - )) + ( stateCurr === STATE_ERROR ) -> STATE_ERROR, + )) + ) diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index d121908..9fde4bf 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -22,12 +22,14 @@ class SlaveSendGenIO extends Bundle{ val isError = Output(Bool()) val stateCurr = Output(UInt(3.W)) + + val flush = Input(Bool()) } -class SlaveSendGen extends Module{ +class SlaveSendGen extends Module with RequireAsyncReset{ val io: SlaveSendGenIO = IO(new SlaveSendGenIO) @@ -60,7 +62,7 @@ class SlaveSendGen extends Module{ - crc.reset := reset.asBool | stateCurr === STATE_IDLE + crc.io.flush := stateCurr === STATE_IDLE | io.flush @@ -112,30 +114,33 @@ class SlaveSendGen extends Module{ assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) ) - stateNext := Mux1H(Seq( - (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), - (stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( - frameInfo.frameStyle === FRAME_STYLE_COMMON, - Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), - STATE_CRC ), - STATE_FRAME_HEADER), STATE_FRAME_HEADER ), - (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), - - (stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire, - Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文 - STATE_SUBMSG_DATA ), - - (stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire, - Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾 - Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC - Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 - STATE_SUBMSG_TAIL - ), STATE_SUBMSG_TAIL ), + stateNext := + Mux( io.flush, STATE_IDLE, + Mux1H(Seq( + (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), + (stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( + frameInfo.frameStyle === FRAME_STYLE_COMMON, + Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), + STATE_CRC ), + STATE_FRAME_HEADER), STATE_FRAME_HEADER ), + (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), + + (stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire, + Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文 + STATE_SUBMSG_DATA ), + + (stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire, + Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾 + Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC + Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 + STATE_SUBMSG_TAIL + ), STATE_SUBMSG_TAIL ), - (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), - // (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), - (stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), - )) + (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), + // (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), + (stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), + )) + ) io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U) io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U) diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index bfd9801..c8e6b96 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -28,7 +28,7 @@ class RegAccessInterfaceIO extends Bundle{ val isEnR = Output(Bool()) } -abstract class SpiInterfaceBase extends Module{ +abstract class SpiInterfaceBase extends Module with RequireAsyncReset{ val io = IO(new RegAccessInterfaceIO) val sck = Wire(Bool()) diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 87340ba..e04999d 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -1,14 +1,12 @@ package test -import MAC._ + import BACK._ -import Switch._ + import chisel3._ import chisel3.stage._ -import freechips.rocketchip.diplomacy._ -import org.chipsalliance.cde.config._ From 72fe230200fc35651169294daa67bb4c453186b3 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 26 Aug 2025 10:30:12 +0800 Subject: [PATCH 03/11] =?UTF-8?q?=E5=B0=9D=E8=AF=95=E6=8A=8ACDR=E6=8F=90?= =?UTF-8?q?=E5=88=B0=E9=A1=B6=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MstSlvSwitch.scala | 472 ++++++++++++++++++ src/main/scala/backBoard/shin/ShinTop.scala | 436 +--------------- 2 files changed, 483 insertions(+), 425 deletions(-) create mode 100644 src/main/scala/backBoard/shin/MstSlvSwitch.scala diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala new file mode 100644 index 0000000..54041bf --- /dev/null +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -0,0 +1,472 @@ +package BACK + +import chisel3._ +import chisel3.util._ + + +class MstSlvSwitchIO extends Bundle{ + + val dDatIn = Input(Bool()) + val dDatOut = Output(Bool()) + val uDatIn = Input(Bool()) + val uDatOut = Output(Bool()) + + val multiCLK = Input(Vec(16, Bool())) + + val iqspi = new QSPIInterfaceIO + val ospi = new SSPIInterfaceIO + val oqspi = new QSPIInterfaceIO + + val iSync = Output(Vec(4, Bool())) + + val isSoftReset = Output(Bool()) + + val interrupt = Output(Bool()) + + val latchPin = Input(Vec(2, Bool())) + val hwSerial = Input(UInt(48.W)) + val uniCode = Input(UInt(64.W)) + + val pllCtrl = Output(UInt(32.W)) + val xtal = Output(UInt(12.W)) + val anamuxSel = Output(UInt(5.W)) + val ldo2p5 = Output(UInt(8.W)) + val ldo1p1 = Output(UInt(8.W)) + val refTop = Output(UInt(3.W)) + val bias = Output(UInt(2.W)) + + val spiSel = Output(UInt(2.W)) +} + + + + + + +abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ + + val io: MstSlvSwitchIO = IO(new MstSlvSwitchIO) + + val slaveParser = Module(new SlaveParser ) + val masterParser = Module(new MasterParser) + + + + + + + val interface = Module(new Interface) + + interface.io.latchPin := io.latchPin + interface.io.uniCode := io.uniCode + interface.io.hwSerial := io.hwSerial + + interface.io.intTransEnd(0) := downCDRIn.io.axis.fire & downCDRIn.io.axis.bits.tlast + interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast + interface.io.intTransEnd(2) := upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast + interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast + + io.isSoftReset := interface.io.isSoftReset + io.interrupt := interface.io.interrupt + + io.ospi <> interface.io.ospi + io.iqspi <> interface.io.iqspi + io.oqspi <> interface.io.oqspi + + io.iSync := interface.io.sync + + + io.pllCtrl := interface.io.cReg.pllCtrl + io.xtal := interface.io.cReg.xtal + io.anamuxSel := interface.io.cReg.anamuxSel + io.ldo2p5 := interface.io.cReg.ldo2p5 + io.ldo1p1 := interface.io.cReg.ldo1p1 + io.refTop := interface.io.cReg.refTop + io.bias := interface.io.cReg.bias + + io.spiSel := interface.io.cReg.spiSel + + val sram = Seq( + for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, + for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, + ) + + + val smUnit = Seq( + Module( new SMUnit(depth = 4) ), + Module( new SMUnit(depth = 4) ), + Module( new SMUnit(depth = 4) ), + Module( new SMUnit(depth = 4) ), + Module( new SMUnit(depth = 2) ), + Module( new SMUnit(depth = 2) ), + Module( new SMUnit(depth = 2) ), + Module( new SMUnit(depth = 2) ), + ) + + val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq + val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq + + + smUnit(0).io.enq := lvdsSMEnq(0) + smUnit(2).io.enq := lvdsSMEnq(1) + smUnit(4).io.enq := lvdsSMEnq(2) + smUnit(6).io.enq := lvdsSMEnq(3) + + smUnit(1).io.deq := lvdsSMDeq(0) + smUnit(3).io.deq := lvdsSMDeq(1) + smUnit(5).io.deq := lvdsSMDeq(2) + smUnit(7).io.deq := lvdsSMDeq(3) + + smUnit(0).io.sram_r <> interface.io.sram_r(0) + smUnit(2).io.sram_r <> interface.io.sram_r(1) + smUnit(4).io.sram_r <> interface.io.sram_r(2) + smUnit(6).io.sram_r <> interface.io.sram_r(3) + + smUnit(1).io.sram_w := interface.io.sram_w(0) + smUnit(3).io.sram_w := interface.io.sram_w(1) + smUnit(5).io.sram_w := interface.io.sram_w(2) + smUnit(7).io.sram_w := interface.io.sram_w(3) + + smUnit(0).io.deq := interface.io.dSMdeq(0) + smUnit(2).io.deq := interface.io.dSMdeq(1) + smUnit(4).io.deq := interface.io.dSMdeq(2) + smUnit(6).io.deq := interface.io.dSMdeq(3) + + + smUnit(1).io.enq := interface.io.uSMenq(0) + smUnit(3).io.enq := interface.io.uSMenq(1) + smUnit(5).io.enq := interface.io.uSMenq(2) + smUnit(7).io.enq := interface.io.uSMenq(3) + + for( i <- 0 until 8 ){ + interface.io.smUsedDepth(i) := smUnit(i).io.cnt + smUnit(i).io.flush := interface.io.isSMReset(i) + } + + + for( i <- 0 until 4 ){ + for( j <- 0 until 4 ){ + sram(i)(j).io.clockr := clock.asBool + sram(i)(j).io.clockw := clock.asBool + + smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar + sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw + sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw + sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw + sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr + sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr + } + } + + for( i <- 4 until 8 ){ + for( j <- 0 until 2 ){ + sram(i)(j).io.clockr := clock.asBool + sram(i)(j).io.clockw := clock.asBool + + smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar + sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw + sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw + sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw + sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr + sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr + } + } + + + + + //default + { + smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) + smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) + smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) + smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) + + smUnit(1).io.sram_r.enr := false.B + smUnit(3).io.sram_r.enr := false.B + smUnit(5).io.sram_r.enr := false.B + smUnit(7).io.sram_r.enr := false.B + smUnit(1).io.sram_r.addrr := 0.U + smUnit(3).io.sram_r.addrr := 0.U + smUnit(5).io.sram_r.addrr := 0.U + smUnit(7).io.sram_r.addrr := 0.U + + slaveParser.io.sram_r(0).datar := 0.U + slaveParser.io.sram_r(1).datar := 0.U + slaveParser.io.sram_r(2).datar := 0.U + slaveParser.io.sram_r(3).datar := 0.U + masterParser.io.sram_r.datar := 0.U + + downCDRIn.io.axis.ready := false.B + slaveParser.io.downIn.valid := false.B + slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + + slaveParser.io.downOut.ready := false.B + masterParser.io.downOut.ready := false.B + downCDROut.io.axis.valid := false.B + downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + + upCDRIn.io.axis.ready := false.B + slaveParser.io.upIn.valid := false.B + slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + masterParser.io.upIn.valid := false.B + masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + + slaveParser.io.upOut.ready := false.B + upCDROut.io.axis.valid := false.B + upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + + interface.io.mstDeltaTime := 0.U + + interface.io.slvDeltaTime := 0.U + interface.io.deltaFinal := 0.U + + interface.io.intMstTrig(0) := false.B + interface.io.intMstTrig(1) := false.B + + interface.io.intSlvTrig(0) := false.B + interface.io.intSlvTrig(1) := false.B + interface.io.intSlvTrig(2) := false.B + interface.io.intSlvTrig(3) := false.B + interface.io.intSlvTrig(4) := false.B + interface.io.intSlvTrig(5) := false.B + interface.io.intSlvTrig(6) := false.B + interface.io.intSlvTrig(7) := false.B + + interface.io.intHWTrig(0) := false.B + interface.io.intHWTrig(1) := false.B + + interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle) + interface.io.upRecStat := 0.U.asTypeOf(new Stat_IO_Bundle) + } + +} + + +trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => + + when( interface.io.cReg.modeSel === true.B ){ + masterParser.io.downOut <> downCDROut.io.axis + masterParser.io.upIn <> upCDRIn.io.axis + } + + when( interface.io.cReg.modeSel === true.B ){ + + when( interface.io.txReq.bits.rxSM === 0.U ){ + smUnit(0).io.sram_w := masterParser.io.sram_w + lvdsSMEnq(0) := masterParser.io.rxEnq + } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){ + smUnit(2).io.sram_w := masterParser.io.sram_w + lvdsSMEnq(1) := masterParser.io.rxEnq + } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){ + smUnit(4).io.sram_w := masterParser.io.sram_w + lvdsSMEnq(2) := masterParser.io.rxEnq + } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){ + smUnit(6).io.sram_w := masterParser.io.sram_w + lvdsSMEnq(3) := masterParser.io.rxEnq + } + + when( interface.io.txReq.bits.txSM === 0.U ){ + smUnit(1).io.sram_r <> masterParser.io.sram_r + lvdsSMDeq(0) := masterParser.io.txDeq + } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){ + smUnit(3).io.sram_r <> masterParser.io.sram_r + lvdsSMDeq(1) := masterParser.io.txDeq + } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){ + smUnit(5).io.sram_r <> masterParser.io.sram_r + lvdsSMDeq(2) := masterParser.io.txDeq + } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){ + smUnit(7).io.sram_r <> masterParser.io.sram_r + lvdsSMDeq(3) := masterParser.io.txDeq + } + + + + interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp + interface.io.intMstTrig(0) := masterParser.io.txDeq + interface.io.intMstTrig(1) := masterParser.io.rxEnq + + interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle) + interface.io.upRecStat := masterParser.io.upRecStat + + } + + masterParser.io.req := interface.io.txReq.valid + // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength + + // io.rsp := masterParser.io.rsp + + masterParser.io.cReg := interface.io.cReg + masterParser.io.mReg := interface.io.mReg + + +} + + +trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => + + when( interface.io.cReg.modeSel === false.B ){ + slaveParser.io.downIn <> downCDRIn.io.axis + downCDROut.io.axis <> slaveParser.io.downOut + slaveParser.io.upIn <> upCDRIn.io.axis + upCDROut.io.axis <> slaveParser.io.upOut + } + + slaveParser.io.cReg := interface.io.cReg + slaveParser.io.sReg := interface.io.sReg + + when( interface.io.cReg.modeSel === false.B ){ + smUnit(0).io.sram_w := slaveParser.io.sram_w(0) + smUnit(2).io.sram_w := slaveParser.io.sram_w(1) + smUnit(4).io.sram_w := slaveParser.io.sram_w(2) + smUnit(6).io.sram_w := slaveParser.io.sram_w(3) + + smUnit(1).io.sram_r <> slaveParser.io.sram_r(0) + smUnit(3).io.sram_r <> slaveParser.io.sram_r(1) + smUnit(5).io.sram_r <> slaveParser.io.sram_r(2) + smUnit(7).io.sram_r <> slaveParser.io.sram_r(3) + + lvdsSMEnq(0) := slaveParser.io.dSMenq(0) + lvdsSMEnq(1) := slaveParser.io.dSMenq(1) + lvdsSMEnq(2) := slaveParser.io.dSMenq(2) + lvdsSMEnq(3) := slaveParser.io.dSMenq(3) + + lvdsSMDeq(0) := slaveParser.io.uSMdeq(0) + lvdsSMDeq(1) := slaveParser.io.uSMdeq(1) + lvdsSMDeq(2) := slaveParser.io.uSMdeq(2) + lvdsSMDeq(3) := slaveParser.io.uSMdeq(3) + + interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp + interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime + interface.io.deltaFinal := slaveParser.io.deltaFinal + + interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0) + interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0) + interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1) + interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1) + interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2) + interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2) + interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3) + interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3) + + interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0) + interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1) + + + interface.io.downRecStat := slaveParser.io.downRecStat + interface.io.upRecStat := slaveParser.io.upRecStat + + } + + slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) + slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) + downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + + interface.io.lvds <> slaveParser.io.lvds + + interface.io.localDevIndex := slaveParser.io.localDevIndex + + //从站链路寄存器 + // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft + // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify + // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev + interface.io.isDevOnRight := slaveParser.io.isDevOnRight + interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify + interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev +} + + +trait MstSlvSwitchDog{ this: MstSlvSwitchBase => + + //看门狗1~16，SM监控 + val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) } + val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) } + + for( i <- 0 until 8 ){ + when( smUnit(i).io.enq ){ + isWdtSMEnable(2*i) := false.B + } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){ + isWdtSMEnable(2*i) := true.B + } + + when( smUnit(i).io.deq ){ + isWdtSMEnable(2*i + 1) := false.B + } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){ + isWdtSMEnable(2*i + 1) := true.B + } + } + + for( i <- 0 until 16 ){ + when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){ + wdtSMCnt(i) := wdtSMCnt(i) + 1.U + } .elsewhen( ~isWdtSMEnable(i) || (wdtSMCnt(i) >= interface.io.cReg.wdtTarCnt(i+1)) ){ + wdtSMCnt(i) := 0.U + } + + // assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" ) + + interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1) + } + + //看门狗0 发送后回包是否超时 + val isWdtRec2RtnEnable = RegInit(false.B) + val wdtRec2RtnCnt = Reg(UInt(32.W)) + + when( + (upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast) | + ~interface.io.cReg.wdtEnable.extract(0) + ){ + isWdtRec2RtnEnable := false.B + } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ + isWdtRec2RtnEnable := true.B + } + + when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){ + wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U + } .elsewhen( ~isWdtRec2RtnEnable || (wdtRec2RtnCnt >= interface.io.cReg.wdtTarCnt(0)) ){ + wdtRec2RtnCnt := 0.U + } + + // assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" ) + + interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0) + + //看门狗17 + val wdtRec2RecCnt = Reg(UInt(32.W)) + + when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){ + wdtRec2RecCnt := wdtRec2RecCnt + 1.U + } .elsewhen( + ~interface.io.cReg.wdtEnable.extract(17) || + downCDRIn.io.axis.fire || + (wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17)) + ){ + wdtRec2RecCnt := 0.U + } + + interface.io.wdtTrigger(17) := wdtRec2RecCnt === interface.io.cReg.wdtTarCnt(17) + +} + + + +class MstSlvSwitch extends MstSlvSwitchBase +with MstSlvSwitchMaster +with MstSlvSwitchSlave +with MstSlvSwitchWatchDog{ + + + + + + +} diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 4cb6d89..e9b548f 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.util._ + class ShinTopIO extends Bundle{ val dDatIn = Input(Bool()) @@ -17,15 +18,9 @@ class ShinTopIO extends Bundle{ val ospi = new SSPIInterfaceIO val oqspi = new QSPIInterfaceIO - // val rsp = Valid(new Bundle{ - // val isError = Bool() - // }) - val iSync = Output(Vec(4, Bool())) - val oSync = Output(Vec(4, Bool())) val isSoftReset = Output(Bool()) - val ledTest = Output(UInt(8.W)) val interrupt = Output(Bool()) @@ -45,438 +40,23 @@ class ShinTopIO extends Bundle{ } +class ShinTop extends Module with RequireAsyncReset{ - - -abstract class ShinTopBase extends Module with RequireAsyncReset{ - - val io: ShinTopIO = IO(new ShinTopIO) - - val slaveParser = Module(new SlaveParser ) - val masterParser = Module(new MasterParser) - - val downCDRIn = Module(new MPCDRIn) - val upCDRIn = Module(new MPCDRIn) - - + downCDRIn.multiCLK := io.multiCLK upCDRIn.multiCLK := io.multiCLK val downCDROut = Module(new CDROut) val upCDROut = Module(new CDROut) + val downCDRIn = Module(new MPCDRIn) + val upCDRIn = Module(new MPCDRIn) - val interface = Module(new Interface) - interface.io.latchPin := io.latchPin - interface.io.uniCode := io.uniCode - interface.io.hwSerial := io.hwSerial - interface.io.intTransEnd(0) := downCDRIn.io.axis.fire & downCDRIn.io.axis.bits.tlast - interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast - interface.io.intTransEnd(2) := upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast - interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast - io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) ) - - io.isSoftReset := interface.io.isSoftReset - io.interrupt := interface.io.interrupt - io.ospi <> interface.io.ospi - io.iqspi <> interface.io.iqspi - io.oqspi <> interface.io.oqspi - - io.iSync := interface.io.sync - io.oSync := interface.io.sync - - io.pllCtrl := interface.io.cReg.pllCtrl - io.xtal := interface.io.cReg.xtal - io.anamuxSel := interface.io.cReg.anamuxSel - io.ldo2p5 := interface.io.cReg.ldo2p5 - io.ldo1p1 := interface.io.cReg.ldo1p1 - io.refTop := interface.io.cReg.refTop - io.bias := interface.io.cReg.bias - - io.spiSel := interface.io.cReg.spiSel - - val sram = Seq( - for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, - for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) }, - ) - - - val smUnit = Seq( - Module( new SMUnit(depth = 4) ), - Module( new SMUnit(depth = 4) ), - Module( new SMUnit(depth = 4) ), - Module( new SMUnit(depth = 4) ), - Module( new SMUnit(depth = 2) ), - Module( new SMUnit(depth = 2) ), - Module( new SMUnit(depth = 2) ), - Module( new SMUnit(depth = 2) ), - ) - - val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq - val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq - - - smUnit(0).io.enq := lvdsSMEnq(0) - smUnit(2).io.enq := lvdsSMEnq(1) - smUnit(4).io.enq := lvdsSMEnq(2) - smUnit(6).io.enq := lvdsSMEnq(3) - - smUnit(1).io.deq := lvdsSMDeq(0) - smUnit(3).io.deq := lvdsSMDeq(1) - smUnit(5).io.deq := lvdsSMDeq(2) - smUnit(7).io.deq := lvdsSMDeq(3) - - smUnit(0).io.sram_r <> interface.io.sram_r(0) - smUnit(2).io.sram_r <> interface.io.sram_r(1) - smUnit(4).io.sram_r <> interface.io.sram_r(2) - smUnit(6).io.sram_r <> interface.io.sram_r(3) - - smUnit(1).io.sram_w := interface.io.sram_w(0) - smUnit(3).io.sram_w := interface.io.sram_w(1) - smUnit(5).io.sram_w := interface.io.sram_w(2) - smUnit(7).io.sram_w := interface.io.sram_w(3) - - smUnit(0).io.deq := interface.io.dSMdeq(0) - smUnit(2).io.deq := interface.io.dSMdeq(1) - smUnit(4).io.deq := interface.io.dSMdeq(2) - smUnit(6).io.deq := interface.io.dSMdeq(3) - - - smUnit(1).io.enq := interface.io.uSMenq(0) - smUnit(3).io.enq := interface.io.uSMenq(1) - smUnit(5).io.enq := interface.io.uSMenq(2) - smUnit(7).io.enq := interface.io.uSMenq(3) - - for( i <- 0 until 8 ){ - interface.io.smUsedDepth(i) := smUnit(i).io.cnt - smUnit(i).io.flush := interface.io.isSMReset(i) - } - - - for( i <- 0 until 4 ){ - for( j <- 0 until 4 ){ - sram(i)(j).io.clockr := clock.asBool - sram(i)(j).io.clockw := clock.asBool - - smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar - sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw - sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw - sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw - sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr - sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr - } - } - - for( i <- 4 until 8 ){ - for( j <- 0 until 2 ){ - sram(i)(j).io.clockr := clock.asBool - sram(i)(j).io.clockw := clock.asBool - - smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar - sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw - sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw - sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw - sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr - sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr - } - } - - - - - //default - { - smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) - smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) - smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) - smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO) - - smUnit(1).io.sram_r.enr := false.B - smUnit(3).io.sram_r.enr := false.B - smUnit(5).io.sram_r.enr := false.B - smUnit(7).io.sram_r.enr := false.B - smUnit(1).io.sram_r.addrr := 0.U - smUnit(3).io.sram_r.addrr := 0.U - smUnit(5).io.sram_r.addrr := 0.U - smUnit(7).io.sram_r.addrr := 0.U - - slaveParser.io.sram_r(0).datar := 0.U - slaveParser.io.sram_r(1).datar := 0.U - slaveParser.io.sram_r(2).datar := 0.U - slaveParser.io.sram_r(3).datar := 0.U - masterParser.io.sram_r.datar := 0.U - - downCDRIn.io.axis.ready := false.B - slaveParser.io.downIn.valid := false.B - slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - - slaveParser.io.downOut.ready := false.B - masterParser.io.downOut.ready := false.B - downCDROut.io.axis.valid := false.B - downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - - upCDRIn.io.axis.ready := false.B - slaveParser.io.upIn.valid := false.B - slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - masterParser.io.upIn.valid := false.B - masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - - slaveParser.io.upOut.ready := false.B - upCDROut.io.axis.valid := false.B - upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - - interface.io.mstDeltaTime := 0.U - - interface.io.slvDeltaTime := 0.U - interface.io.deltaFinal := 0.U - - interface.io.intMstTrig(0) := false.B - interface.io.intMstTrig(1) := false.B - - interface.io.intSlvTrig(0) := false.B - interface.io.intSlvTrig(1) := false.B - interface.io.intSlvTrig(2) := false.B - interface.io.intSlvTrig(3) := false.B - interface.io.intSlvTrig(4) := false.B - interface.io.intSlvTrig(5) := false.B - interface.io.intSlvTrig(6) := false.B - interface.io.intSlvTrig(7) := false.B - - interface.io.intHWTrig(0) := false.B - interface.io.intHWTrig(1) := false.B - - interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle) - interface.io.upRecStat := 0.U.asTypeOf(new Stat_IO_Bundle) - } - -} - - -trait ShinTopMaster{ this: ShinTopBase => - - when( interface.io.cReg.modeSel === true.B ){ - masterParser.io.downOut <> downCDROut.io.axis - masterParser.io.upIn <> upCDRIn.io.axis - } - - when( interface.io.cReg.modeSel === true.B ){ - - when( interface.io.txReq.bits.rxSM === 0.U ){ - smUnit(0).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(0) := masterParser.io.rxEnq - } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){ - smUnit(2).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(1) := masterParser.io.rxEnq - } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){ - smUnit(4).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(2) := masterParser.io.rxEnq - } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){ - smUnit(6).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(3) := masterParser.io.rxEnq - } - - when( interface.io.txReq.bits.txSM === 0.U ){ - smUnit(1).io.sram_r <> masterParser.io.sram_r - lvdsSMDeq(0) := masterParser.io.txDeq - } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){ - smUnit(3).io.sram_r <> masterParser.io.sram_r - lvdsSMDeq(1) := masterParser.io.txDeq - } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){ - smUnit(5).io.sram_r <> masterParser.io.sram_r - lvdsSMDeq(2) := masterParser.io.txDeq - } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){ - smUnit(7).io.sram_r <> masterParser.io.sram_r - lvdsSMDeq(3) := masterParser.io.txDeq - } - - - - interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp - interface.io.intMstTrig(0) := masterParser.io.txDeq - interface.io.intMstTrig(1) := masterParser.io.rxEnq - - interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle) - interface.io.upRecStat := masterParser.io.upRecStat - - } - - masterParser.io.req := interface.io.txReq.valid - // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength - - // io.rsp := masterParser.io.rsp - - masterParser.io.cReg := interface.io.cReg - masterParser.io.mReg := interface.io.mReg - - -} - - -trait ShinTopSlave{ this: ShinTopBase => - - when( interface.io.cReg.modeSel === false.B ){ - slaveParser.io.downIn <> downCDRIn.io.axis - downCDROut.io.axis <> slaveParser.io.downOut - slaveParser.io.upIn <> upCDRIn.io.axis - upCDROut.io.axis <> slaveParser.io.upOut - } - - slaveParser.io.cReg := interface.io.cReg - slaveParser.io.sReg := interface.io.sReg - - when( interface.io.cReg.modeSel === false.B ){ - smUnit(0).io.sram_w := slaveParser.io.sram_w(0) - smUnit(2).io.sram_w := slaveParser.io.sram_w(1) - smUnit(4).io.sram_w := slaveParser.io.sram_w(2) - smUnit(6).io.sram_w := slaveParser.io.sram_w(3) - - smUnit(1).io.sram_r <> slaveParser.io.sram_r(0) - smUnit(3).io.sram_r <> slaveParser.io.sram_r(1) - smUnit(5).io.sram_r <> slaveParser.io.sram_r(2) - smUnit(7).io.sram_r <> slaveParser.io.sram_r(3) - - lvdsSMEnq(0) := slaveParser.io.dSMenq(0) - lvdsSMEnq(1) := slaveParser.io.dSMenq(1) - lvdsSMEnq(2) := slaveParser.io.dSMenq(2) - lvdsSMEnq(3) := slaveParser.io.dSMenq(3) - - lvdsSMDeq(0) := slaveParser.io.uSMdeq(0) - lvdsSMDeq(1) := slaveParser.io.uSMdeq(1) - lvdsSMDeq(2) := slaveParser.io.uSMdeq(2) - lvdsSMDeq(3) := slaveParser.io.uSMdeq(3) - - interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp - interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime - interface.io.deltaFinal := slaveParser.io.deltaFinal - - interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0) - interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0) - interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1) - interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1) - interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2) - interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2) - interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3) - interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3) - - interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0) - interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1) - - - interface.io.downRecStat := slaveParser.io.downRecStat - interface.io.upRecStat := slaveParser.io.upRecStat - - } - - slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) - slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) - downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) - - interface.io.lvds <> slaveParser.io.lvds - - interface.io.localDevIndex := slaveParser.io.localDevIndex - - //从站链路寄存器 - // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft - // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify - // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev - interface.io.isDevOnRight := slaveParser.io.isDevOnRight - interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify - interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev -} - - -trait ShinTopWatchDog{ this: ShinTopBase => - - //看门狗1~16，SM监控 - val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) } - val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) } - - for( i <- 0 until 8 ){ - when( smUnit(i).io.enq ){ - isWdtSMEnable(2*i) := false.B - } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){ - isWdtSMEnable(2*i) := true.B - } - - when( smUnit(i).io.deq ){ - isWdtSMEnable(2*i + 1) := false.B - } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){ - isWdtSMEnable(2*i + 1) := true.B - } - } - - for( i <- 0 until 16 ){ - when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){ - wdtSMCnt(i) := wdtSMCnt(i) + 1.U - } .elsewhen( ~isWdtSMEnable(i) || (wdtSMCnt(i) >= interface.io.cReg.wdtTarCnt(i+1)) ){ - wdtSMCnt(i) := 0.U - } - - // assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" ) - - interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1) - } - - //看门狗0 发送后回包是否超时 - val isWdtRec2RtnEnable = RegInit(false.B) - val wdtRec2RtnCnt = Reg(UInt(32.W)) - - when( - (upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast) | - ~interface.io.cReg.wdtEnable.extract(0) - ){ - isWdtRec2RtnEnable := false.B - } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ - isWdtRec2RtnEnable := true.B - } - - when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){ - wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U - } .elsewhen( ~isWdtRec2RtnEnable || (wdtRec2RtnCnt >= interface.io.cReg.wdtTarCnt(0)) ){ - wdtRec2RtnCnt := 0.U - } - - // assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" ) - - interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0) - - //看门狗17 - val wdtRec2RecCnt = Reg(UInt(32.W)) - - when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){ - wdtRec2RecCnt := wdtRec2RecCnt + 1.U - } .elsewhen( - ~interface.io.cReg.wdtEnable.extract(17) || - downCDRIn.io.axis.fire || - (wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17)) - ){ - wdtRec2RecCnt := 0.U - } - - interface.io.wdtTrigger(17) := wdtRec2RecCnt === interface.io.cReg.wdtTarCnt(17) - -} - - - -class ShinTop extends ShinTopBase -with ShinTopMaster -with ShinTopSlave -with ShinTopWatchDog{ when( interface.io.cReg.modeSel === false.B ){ //slave when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 @@ -512,4 +92,10 @@ with ShinTopWatchDog{ + + } + + + + From 6b118fa49864fa5c856adfb248bc4267e1ba8df6 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 26 Aug 2025 11:35:47 +0800 Subject: [PATCH 04/11] =?UTF-8?q?spi=E8=AF=BB0x100=E5=B0=86=E4=BC=9A?= =?UTF-8?q?=E6=9A=82=E5=AD=98=E5=90=8E=E7=BB=AD=E5=AF=84=E5=AD=98=E5=99=A8?= =?UTF-8?q?=E9=98=B2=E6=AD=A2=E8=BF=9B=E4=BD=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 918ed57..59bd942 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -379,13 +379,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ Seq( //本地时钟 (addr === "h100".U ) -> cReg.timeStamp(7,0), - (addr === "h101".U ) -> cReg.timeStamp(15,8), - (addr === "h102".U ) -> cReg.timeStamp(23,16), - (addr === "h103".U ) -> cReg.timeStamp(31,24), - (addr === "h104".U ) -> cReg.timeStamp(39,32), - (addr === "h105".U ) -> cReg.timeStamp(47,40), - (addr === "h106".U ) -> cReg.timeStamp(55,48), - (addr === "h107".U ) -> cReg.timeStamp(63,56), + (addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & addrr === "h100".U), + (addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & addrr === "h100".U), + (addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & addrr === "h100".U), + (addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & addrr === "h100".U), + (addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & addrr === "h100".U), + (addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & addrr === "h100".U), + (addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & addrr === "h100".U), //参考主站时钟 (addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0), From ae99f5801d2c9acb912690faad3eaacb0c47c980 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 26 Aug 2025 15:17:37 +0800 Subject: [PATCH 05/11] =?UTF-8?q?spi=E8=AF=BB=E9=94=81=E5=AE=9A0x118?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 59bd942..a82ac3e 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -379,13 +379,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ Seq( //本地时钟 (addr === "h100".U ) -> cReg.timeStamp(7,0), - (addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & addrr === "h100".U), - (addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & addrr === "h100".U), - (addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & addrr === "h100".U), - (addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & addrr === "h100".U), - (addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & addrr === "h100".U), - (addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & addrr === "h100".U), - (addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & addrr === "h100".U), + (addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & (addrr === "h100".U)), + (addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)), + (addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)), + (addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)), + (addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)), + (addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)), + (addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)), //参考主站时钟 (addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0), @@ -411,13 +411,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ //校准后的时钟 (addr === "h118".U ) -> cReg.recoTimeStamp(7,0), - (addr === "h119".U ) -> cReg.recoTimeStamp(15,8), - (addr === "h11a".U ) -> cReg.recoTimeStamp(23,16), - (addr === "h11b".U ) -> cReg.recoTimeStamp(31,24), - (addr === "h11c".U ) -> cReg.recoTimeStamp(39,32), - (addr === "h11d".U ) -> cReg.recoTimeStamp(47,40), - (addr === "h11e".U ) -> cReg.recoTimeStamp(55,48), - (addr === "h11f".U ) -> cReg.recoTimeStamp(63,56), + (addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), isEnR & (addrr === "h118".U)), + (addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)), + (addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)), + (addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)), + (addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)), + (addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)), + (addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)), (addr === "h120".U ) -> cReg.syncCfg, From b821571218744ca7ad46a7026b7a5b35e716c167 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 26 Aug 2025 17:02:57 +0800 Subject: [PATCH 06/11] =?UTF-8?q?=E5=90=8C=E6=AD=A5=E9=80=BB=E8=BE=91?= =?UTF-8?q?=E6=89=A9=E5=B1=95delta=E4=BD=8D=E5=AE=BD=EF=BC=8C=E4=BD=BF?= =?UTF-8?q?=E7=94=A8=E5=88=86=E6=97=B6=E5=85=B1=E4=BA=AB64=E4=BD=8D?= =?UTF-8?q?=E5=8A=A0=E6=B3=95=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 14 +++--- .../scala/backBoard/shin/SlaveParser.scala | 46 +++++++++++++++---- 2 files changed, 44 insertions(+), 16 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index a82ac3e..9c70cb0 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -138,7 +138,7 @@ class SlaveRegisterBundle extends Bundle{ val slvDeltaTime = UInt(32.W) //从站时间戳差值 - val deltaFinal = UInt(32.W) //当前时间戳与主站时间差 + val deltaFinal = UInt(64.W) //当前时间戳与主站时间差 @@ -183,7 +183,7 @@ class InterfaceIO extends Bundle{ val slvDeltaTime = Input(UInt(32.W)) //从站时间戳差值 val mstDeltaTime = Input(UInt(32.W)) - val deltaFinal = Input(UInt(32.W)) + val deltaFinal = Input(UInt(64.W)) val sync = Output(Vec(4, Bool())) @@ -392,10 +392,10 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === "h109".U & isSlvMode) -> sReg.deltaFinal(15,8), (addr === "h10a".U & isSlvMode) -> sReg.deltaFinal(23,16), (addr === "h10b".U & isSlvMode) -> sReg.deltaFinal(31,24), - // (addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32), - // (addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40), - // (addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48), - // (addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56), + (addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32), + (addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40), + (addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48), + (addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56), //主站发送接收时间差 (addr === "h110".U ) -> cReg.mstDeltaTime(7,0), @@ -963,7 +963,7 @@ trait InterfaceSync{ this: InterfaceBase => sReg.deltaFinal := io.deltaFinal cReg.recoTimeStamp := Mux(isMstMode, cReg.timeStamp, - RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) ) + RegNext( cReg.timeStamp + sReg.deltaFinal ) ) sReg.slvDeltaTime := io.slvDeltaTime diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index e550798..5d09eb4 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -66,7 +66,7 @@ class SlaveParserIO extends Bundle{ val mstDeltaTimeStamp = Output(UInt(32.W)) val slvDeltaTime = Output(UInt(32.W)) - val deltaFinal = Output(UInt(32.W)) + val deltaFinal = Output(UInt(64.W)) val isLoop = Output(Bool()) @@ -812,6 +812,14 @@ trait SlaveParserRW{ this: SlaveParserBase => trait SlaveParserSync{ this: SlaveParserBase => + val addr64_op1 = WireDefault( 0.U(64.W) ) + val addr64_op2 = WireDefault( 0.U(64.W) ) + def subOp2(x:UInt) = ~x + 1.U + val addr64_res = addr64_op1 + addr64_op2 + + val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B})) + assert( PopCount(addrConflict) <= 1.U ) + //下行接收 when( downRecParser.io.subMsgTailReq.fire ){ @@ -837,9 +845,9 @@ trait SlaveParserSync{ this: SlaveParserBase => val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值 val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值 - val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量) - val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量) - val deltaFinal = Reg(UInt(32.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差 + val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量) + val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量) + val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差 // val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器 @@ -860,7 +868,12 @@ trait SlaveParserSync{ this: SlaveParserBase => //更新上行本地时间戳寄存器 when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ upTimeStamp := io.cReg.timeStamp - slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp + + // slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp + addr64_op1 := io.cReg.timeStamp //组合逻辑 + addr64_op2 := subOp2(downTimeStamp) //组合逻辑 + addrConflict(0) := true.B //组合逻辑 + slvDeltaTimeStamp := addr64_res //时序逻辑 } //下行接收 @@ -898,7 +911,13 @@ trait SlaveParserSync{ this: SlaveParserBase => } .elsewhen( syncCnt === 7.U ){ mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) ) } .elsewhen( syncCnt === 8.U ){ - mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp + // mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp + + addr64_op1 := mstTimeStamp //组合逻辑 + addr64_op2 := subOp2(downTimeStamp) //组合逻辑 + addrConflict(1) := true.B //组合逻辑 + mstSlvDeltaTimeStamp := addr64_res //时序逻辑 + mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits ) } .elsewhen( syncCnt === 9.U ){ mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) ) @@ -912,10 +931,19 @@ trait SlaveParserSync{ this: SlaveParserBase => } when( RegNext(isSync) & ~isSync ){ - val deltaMstSlvDeltaTimeStamp_org = mstDeltaTimeStamp - slvDeltaTimeStamp - deltaMstSlvDeltaTimeStamp := Cat( deltaMstSlvDeltaTimeStamp_org.extract(deltaMstSlvDeltaTimeStamp_org.getWidth-1), deltaMstSlvDeltaTimeStamp_org(deltaMstSlvDeltaTimeStamp_org.getWidth-1, 1) ) //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 + // deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 + + addr64_op1 := mstDeltaTimeStamp //组合逻辑 + addr64_op2 := subOp2(slvDeltaTimeStamp) //组合逻辑 + addrConflict(2) := true.B //组合逻辑 + deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑 + } .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){ - deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp + // deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp + addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑 + addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑 + addrConflict(3) := true.B //组合逻辑 + deltaFinal := addr64_res //时序逻辑 } From f8065c79c95f505a6471d8301ab0d9be7672c9c1 Mon Sep 17 00:00:00 2001 From: bacon Date: Mon, 25 Aug 2025 22:43:34 +0800 Subject: [PATCH 07/11] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E5=9F=BA=E7=A1=80?= =?UTF-8?q?=E5=BA=93=E9=87=8C=E7=94=9F=E6=88=90=E4=BB=A3=E7=A0=81=E7=9A=84?= =?UTF-8?q?=E6=96=B9=E5=BC=8F=EF=BC=8C=E5=88=A0=E9=99=A4=E4=B8=8D=E5=BF=85?= =?UTF-8?q?=E8=A6=81=E7=9A=84=E5=BA=9F=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/pyutils/GenPkt.py | 38 +++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/tb/shinTest/pyutils/GenPkt.py b/tb/shinTest/pyutils/GenPkt.py index ee5c759..067fe38 100644 --- a/tb/shinTest/pyutils/GenPkt.py +++ b/tb/shinTest/pyutils/GenPkt.py @@ -57,6 +57,7 @@ class GenPkt(object): self.sub_pkt.append([0, dev_idx, ptype, addr, cmd, len, data]) def gen(self, filename="pkt_verilog_test.v", filetype=0, appendgen=False, gen_name=None): + gen_pkt_type = 0 pkt_len = 4 for sp in self.sub_pkt: if sp[0] != 0: @@ -81,12 +82,14 @@ class GenPkt(object): self.pkt_buf.append(self.pkt_type & 0x3) self.pkt_buf.append(0x3f) self.pkt_buf.append(0xff) + gen_pkt_type = 1 elif (self.pkt_type == 2): pkt_len = len(self.pkt_data) for d in self.pkt_data: self.pkt_buf.append(d) i = pkt_len + gen_pkt_type = 2 #print("-----------------------------", filename, self.pkt_type, pkt_len, self.pkt_buf) else: #for i in range(pkt_len): @@ -106,6 +109,7 @@ class GenPkt(object): pass #elif sp[0] == 0: else: + gen_pkt_type = 3 #设备索引(14bit)+类型(2bit) temp = ((sp[1] & 0x3fff) << 2) | (sp[2] & 0x3) @@ -187,25 +191,25 @@ class GenPkt(object): else: define_str = define_str + gen_name + if gen_pkt_type != 0: + f.write(define_str + "_len \t%d\n"%(pkt_len)) + f.write(define_str + "_sm(array) \\\n\tarray``[%d]=8'h%02X;\\\n\tarray``[%d]=8'h%02X;\n"%( + 3, pkt_len & 0xff, + 4, pkt_len >> 8 + )) - f.write(define_str + "_len \t%d\n"%(pkt_len)) - f.write(define_str + "_sm(array) \\\n\tarray``[%d]=8'h%02X;\\\n\tarray``[%d]=8'h%02X;\n"%( - 3, pkt_len & 0xff, - 4, pkt_len >> 8 - )) - - f.write(define_str + "(array) \\\n") - for _k in range(i): - if _k < (i - 1): - if type(self.pkt_buf[_k]) == int: - f.write("\tarray``[%d]=8'h%02X;\\\n"%(3 + _k, self.pkt_buf[_k])) + f.write(define_str + "(array) \\\n") + for _k in range(i): + if _k < (i - 1): + if type(self.pkt_buf[_k]) == int: + f.write("\tarray``[%d]=8'h%02X;\\\n"%(3 + _k, self.pkt_buf[_k])) + else: + f.write("\tarray``[%d]=%s;\\\n"%(3 + _k, self.pkt_buf[_k])) else: - f.write("\tarray``[%d]=%s;\\\n"%(3 + _k, self.pkt_buf[_k])) - else: - if type(self.pkt_buf[_k]) == int: - f.write("\tarray``[%d]=8'h%02X;\n"%(3 + _k, self.pkt_buf[_k])) - else: - f.write("\tarray``[%d]=%s;\n"%(3 + _k, self.pkt_buf[_k])) + if type(self.pkt_buf[_k]) == int: + f.write("\tarray``[%d]=8'h%02X;\n"%(3 + _k, self.pkt_buf[_k])) + else: + f.write("\tarray``[%d]=%s;\n"%(3 + _k, self.pkt_buf[_k])) for md in self.sub_pkt: if md[0] == 2: From 1fe1959f8c406f0dbd5adb8ecad6d6abe8e41e1d Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 26 Aug 2025 17:35:30 +0800 Subject: [PATCH 08/11] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=96=B0=E7=9A=84?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B,=E6=B5=8B=E8=AF=95sync?= =?UTF-8?q?=E5=AF=84=E5=AD=98=E5=99=A8=E7=BB=84=E7=9A=84=E6=97=B6=E9=97=B4?= =?UTF-8?q?=E8=AF=BB=E5=8F=96,=E4=BB=A5=E5=85=8D=E5=8F=91=E7=94=9F?= =?UTF-8?q?=E8=BF=9B=E4=BD=8D=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 1 + tb/shinTest/gen_pkt.py | 6 +- tb/shinTest/testcase/base.py | 98 ++++++++++++++++++- tb/shinTest/testcase/environment.py | 44 ++++----- tb/shinTest/testcase/errorPkt.py | 8 ++ .../testcase_result/base_tc02_result.log | 2 +- .../testcase_result/base_tc08_result.log | 8 +- 7 files changed, 135 insertions(+), 32 deletions(-) diff --git a/Makefile b/Makefile index 7125c4a..8b0779e 100644 --- a/Makefile +++ b/Makefile @@ -56,6 +56,7 @@ testShin: testFilter: ./tb/shinTest/test_filter.py + vcdFilter: gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 & diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 205764e..c80177b 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -4,8 +4,9 @@ from pyutils import * from testcase import environment, readregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac if __name__ == '__main__': - environment.gen_slv_dev_num(10) + environment.gen_slv_dev_num(4) environment.bringup() + #add_tc_2_runlist(errorPkt.tc1()) #add_tc_2_runlist(errorPkt.tc2()) #add_tc_2_runlist(errorPkt.tc3()) @@ -13,7 +14,7 @@ if __name__ == '__main__': #add_tc_2_runlist(errorPkt.tc5()) #add_tc_2_runlist(errorPkt.tc6()) - add_tc_2_runlist(base.tc1()) + #add_tc_2_runlist(base.tc1()) #add_tc_2_runlist(base.tc2()) #add_tc_2_runlist(base.tc3()) #add_tc_2_runlist(base.tc4()) @@ -38,6 +39,7 @@ if __name__ == '__main__': #add_tc_2_runlist(base.tc23()) #add_tc_2_runlist(base.tc24()) #add_tc_2_runlist(base.tc25()) + add_tc_2_runlist(base.tc26()) #add_tc_2_runlist(broadcast.tc1()) #add_tc_2_runlist(broadcast.tc2()) diff --git a/tb/shinTest/testcase/base.py b/tb/shinTest/testcase/base.py index 6e0b106..e766e24 100644 --- a/tb/shinTest/testcase/base.py +++ b/tb/shinTest/testcase/base.py @@ -483,15 +483,23 @@ def tc8(): genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des) +genIFRwDataCode(0, 0x78, False, 4) + +genIFRwDataCode(0, 0x40, True, 4, [0x01, 0x00, 0x66, 0x79]) +genIFRwDataCode(2, 0x40, True, 4, [0x01, 0x00, 0x66, 0x79]) + +"\n#5000\n" +genIFRwDataCode(0, 0x09, True, 1, [0, ], False, iface=1) +genIFRwDataCode(2, 0x09, True, 1, [0, ], False, iface=1) + + +genMessageCode("--读取中断") +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(2, 0x74, False, 4) - +genIFRwDataCode(0, 0x40, False, 4) - +genIFRwDataCode(2, 0x40, False, 4) + + +genMessageCode("--读取中断使能") + +genIFRwDataCode(0, 0x70, False, 4) + +genIFRwDataCode(2, 0x70, False, 4) + + +genMessageCode("--配置主从站") +genIFRwDataCode(0, 0x00, True, 1, main_dev) +genIFRwDataCode(2, 0x00, True, 1, slave_dev) ) @@ -515,6 +523,10 @@ def tc8(): +genMessageCode("--清除中断") +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + + +genMessageCode("--配置中断模式") + +genIFRwDataCode(0, 0x7c, True, 2, [0x00, 0x81]) + +genIFRwDataCode(2, 0x7c, True, 2, [0x00, 0x81]) ) genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) @@ -1721,3 +1733,85 @@ def tc25(): return gen_file_def + +def tc26(): + genPkt = GenPkt() + + gen_file_def = "base_tc26" + sm_idx = 0 + tc_des = "读取内部的时钟，看看是否有进位问题，导致读取的错误或不可靠。\\n" + + + #------------------------------------------------------------------------- + #>>>>>>普通数据包 sm1，2个读 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + genPkt.addSubPkt(0x00, 0, 0x00, 0xc, 12, [0, ] * 12) + + + sm_idx = 1 + genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des) + +genEnableInsertTimeCode(0xa)) + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + + +genIFRwDataCode(2, 0x800, False, 0x10) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--清除中断") + +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--读取时间1") + +genIFRwDataCode(0, 0x100, False, 32) + +genIFRwDataCode(1, 0x100, False, 32) + +genIFRwDataCode(2, 0x100, False, 32) + +genIFRwDataCode(3, 0x100, False, 32) + +genIFRwDataCode(4, 0x100, False, 32) + + + +"#8000\n" + +genMessageCode("--读取时间2") + +genIFRwDataCode(0, 0x100, False, 32) + +genIFRwDataCode(1, 0x100, False, 32) + +genIFRwDataCode(2, 0x100, False, 32) + +genIFRwDataCode(3, 0x100, False, 32) + +genIFRwDataCode(4, 0x100, False, 32) + + + +genMessageCode("--读取时间3") + +genIFRwDataCode(0, 0x100, False, 8) + +genIFRwDataCode(0, 0x118, False, 8) + +genIFRwDataCode(1, 0x118, False, 8) + +genIFRwDataCode(2, 0x118, False, 8) + +genIFRwDataCode(3, 0x118, False, 8) + +genIFRwDataCode(4, 0x118, False, 8) + + + +genTcEndFrameCode(gen_file_def)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + return gen_file_def + diff --git a/tb/shinTest/testcase/environment.py b/tb/shinTest/testcase/environment.py index 4d06940..eddc305 100644 --- a/tb/shinTest/testcase/environment.py +++ b/tb/shinTest/testcase/environment.py @@ -100,10 +100,6 @@ def bringup(): genPkt.addBeforeExc(genMessageCode("--设置环境，进行第二次嗅探")) - int_data=[0x00, 0x81] - clear_int = [0xff, 0xff, 0xff, 0xff] - main_int_en = [0x03, 0x00, 0x00, 0xf0] - slave_int_en= [0x00, 0x00, 0x00, 0xf0] genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx) +genWriteTransPktCode(gen_file_def_ap, sm_idx) @@ -117,25 +113,25 @@ def bringup(): +genIFRwDataCode(4, 0xc0, False, 4) +genMessageCode("--使能中断") - +genIFRwDataCode(0, 0x70, True, 4, main_int_en) - +genIFRwDataCode(1, 0x70, True, 4, slave_int_en) - +genIFRwDataCode(2, 0x70, True, 4, slave_int_en) - +genIFRwDataCode(3, 0x70, True, 4, slave_int_en) - +genIFRwDataCode(4, 0x70, True, 4, slave_int_en) + +genIFRwDataCode(0, 0x70, True, 4, [0x03, 0x00, 0x00, 0xf0]) + +genIFRwDataCode(1, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0]) + +genIFRwDataCode(2, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0]) + +genIFRwDataCode(3, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0]) + +genIFRwDataCode(4, 0x70, True, 4, [0x00, 0x00, 0x00, 0xf0]) +genMessageCode("--设置中断为脉冲模式") - +genIFRwDataCode(0, 0x7c, True, 2, int_data) - +genIFRwDataCode(1, 0x7c, True, 2, int_data) - +genIFRwDataCode(2, 0x7c, True, 2, int_data) - +genIFRwDataCode(3, 0x7c, True, 2, int_data) - +genIFRwDataCode(4, 0x7c, True, 2, int_data) + +genIFRwDataCode(0, 0x7c, True, 2, [0x00, 0x81]) + +genIFRwDataCode(1, 0x7c, True, 2, [0x00, 0x81]) + +genIFRwDataCode(2, 0x7c, True, 2, [0x00, 0x81]) + +genIFRwDataCode(3, 0x7c, True, 2, [0x00, 0x81]) + +genIFRwDataCode(4, 0x7c, True, 2, [0x00, 0x81]) +genMessageCode("--清除中断") - +genIFRwDataCode(0, 0x78, True, 4, clear_int) - +genIFRwDataCode(1, 0x78, True, 4, clear_int) - +genIFRwDataCode(2, 0x78, True, 4, clear_int) - +genIFRwDataCode(3, 0x78, True, 4, clear_int) - +genIFRwDataCode(4, 0x78, True, 4, clear_int) + +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genMessageCode("--读取中断状态") +genIFRwDataCode(0, 0x74, False, 4) @@ -145,11 +141,11 @@ def bringup(): +genIFRwDataCode(4, 0x74, False, 4) +genMessageCode("--清除中断") - +genIFRwDataCode(0, 0x78, True, 4, clear_int) - +genIFRwDataCode(1, 0x78, True, 4, clear_int) - +genIFRwDataCode(2, 0x78, True, 4, clear_int) - +genIFRwDataCode(3, 0x78, True, 4, clear_int) - +genIFRwDataCode(4, 0x78, True, 4, clear_int) + +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genMessageCode("--读取中断状态") +genIFRwDataCode(0, 0x74, False, 4) diff --git a/tb/shinTest/testcase/errorPkt.py b/tb/shinTest/testcase/errorPkt.py index 0b12991..59b14b3 100644 --- a/tb/shinTest/testcase/errorPkt.py +++ b/tb/shinTest/testcase/errorPkt.py @@ -160,18 +160,22 @@ def tc2(): +genTrgTransPktCode(gen_file_def_ap, sm_idx) +genReadAckPktCode(gen_file_def_ap, sm_idx) + +"\n#50000\n" + +genMessageCode("--读取中断") +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(1, 0x74, False, 4) +genIFRwDataCode(2, 0x74, False, 4) +genIFRwDataCode(3, 0x74, False, 4) +genIFRwDataCode(4, 0x74, False, 4) + +genMessageCode("--清除中断") +genIFRwDataCode(0, 0x78, True, 4, clear_int) +genIFRwDataCode(1, 0x78, True, 4, clear_int) +genIFRwDataCode(2, 0x78, True, 4, clear_int) +genIFRwDataCode(3, 0x78, True, 4, clear_int) +genIFRwDataCode(4, 0x78, True, 4, clear_int) + +genMessageCode("--读取中断") +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(1, 0x74, False, 4) +genIFRwDataCode(2, 0x74, False, 4) @@ -222,18 +226,22 @@ def tc3(): +genIFRwDataCode(0, 0x22, True, 2, [0xff, 0xff]) +genIFRwDataCode(0, 0x22, False, 2) + +"\n#50000\n" + +genMessageCode("--读取中断") +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(1, 0x74, False, 4) +genIFRwDataCode(2, 0x74, False, 4) +genIFRwDataCode(3, 0x74, False, 4) +genIFRwDataCode(4, 0x74, False, 4) + +genMessageCode("--清除中断") +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genMessageCode("--读取中断") +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(1, 0x74, False, 4) +genIFRwDataCode(2, 0x74, False, 4) diff --git a/tb/shinTest/testcase_result/base_tc02_result.log b/tb/shinTest/testcase_result/base_tc02_result.log index 446b2e4..3f88a55 100644 --- a/tb/shinTest/testcase_result/base_tc02_result.log +++ b/tb/shinTest/testcase_result/base_tc02_result.log @@ -2,7 +2,7 @@ 16'h0316 8'h00 16'h0002 8'h8c 8'h00 16'h3000 8'h00 16'h008c 8'h08 8'h80 8'h00 8'h00 8'h00 8'h04 8'h00 8'h00 8'hd0 8'h80 8'h00 8'h01 8'h02 8'h03 8'h04 8'h05 8'h06 8'h07 8'h08 8'h09 8'h0a 8'h0b 8'h0c 8'h0d 8'h0e 8'h0f 8'h10 8'h11 8'h12 8'h13 8'h14 8'h15 8'h16 8'h17 8'h18 8'h19 8'h1a 8'h1b 8'h1c 8'h1d 8'h1e 8'h1f 8'h20 8'h21 8'h22 8'h23 8'h24 8'h25 8'h26 8'h27 8'h28 8'h29 8'h2a 8'h2b 8'h2c 8'h2d 8'h2e 8'h2f 8'h30 8'h31 8'h32 8'h33 8'h34 8'h35 8'h36 8'h37 8'h38 8'h39 8'h3a 8'h3b 8'h3c 8'h3d 8'h3e 8'h3f 8'h40 8'h41 8'h42 8'h43 8'h44 8'h45 8'h46 8'h47 8'h48 8'h49 8'h4a 8'h4b 8'h4c 8'h4d 8'h4e 8'h4f 8'h50 8'h51 8'h52 8'h53 8'h54 8'h55 8'h56 8'h57 8'h58 8'h59 8'h5a 8'h5b 8'h5c 8'h5d 8'h5e 8'h5f 8'h60 8'h61 8'h62 8'h63 8'h64 8'h65 8'h66 8'h67 8'h68 8'h69 8'h6a 8'h6b 8'h6c 8'h6d 8'h6e 8'h6f 8'h70 8'h71 8'h72 8'h73 8'h74 8'h75 8'h76 8'h77 8'h78 8'h79 8'h7a 8'h7b 8'h7c 8'h7d 8'h7e 8'h7f 8'h00 8'h00 16'h0020 8'h00 16'h0001 8'h15 -16'h2800 8'h01 16'h008c 8'h08 8'h80 8'h00 8'h04 8'h00 8'h04 8'h00 8'h00 8'hd0 8'h80 8'h02 8'h01 8'h02 8'h03 8'h04 8'h05 8'h06 8'h07 8'h5d 8'h09 8'h0f 8'h0b 8'h0c 8'h0d 8'h0e 8'h0f 8'h10 8'h11 8'h12 8'h13 8'h14 8'h15 8'h16 8'h17 8'h18 8'h19 8'h1a 8'h1b 8'h1c 8'h1d 8'h1e 8'h1f 8'h20 8'h21 8'h22 8'h23 8'h24 8'h25 8'h26 8'h27 8'h28 8'h29 8'h2a 8'h2b 8'h2c 8'h2d 8'h2e 8'h2f 8'h30 8'h31 8'h32 8'h33 8'h34 8'h35 8'h36 8'h37 8'h38 8'h39 8'h3a 8'h3b 8'h3c 8'h3d 8'h3e 8'h3f 8'h40 8'h41 8'h42 8'h43 8'h5d 8'hc5 8'h46 8'hc7 8'h5d 8'h4d 8'h4a 8'h4b 8'h4c 8'h4d 8'h4e 8'h4f 8'h50 8'hd7 8'hd7 8'h53 8'h54 8'h55 8'h56 8'h57 8'h58 8'h59 8'h5a 8'h5b 8'h5c 8'h5d 8'h5e 8'h5f 8'h60 8'h61 8'h62 8'h63 8'h64 8'h65 8'h66 8'h67 8'h68 8'h69 8'h6a 8'h6b 8'h6c 8'h6d 8'h6e 8'h6f 8'h70 8'h71 8'h72 8'hf3 8'h74 8'h75 8'h77 8'h77 8'h78 8'h79 8'h7a 8'h7b 8'h7c 8'hfd 8'h7e 8'h7f 8'h00 8'h04 +16'h2800 8'h01 16'h008c 8'h08 8'h80 8'h00 8'h04 8'h00 8'h04 8'h00 8'h00 8'hd0 8'h80 8'h02 8'h01 8'h02 8'h03 8'h04 8'h05 8'h06 8'h07 8'h5d 8'h09 8'h0f 8'h0b 8'h0c 8'h0d 8'h0e 8'h0f 8'h10 8'h11 8'h12 8'h13 8'h14 8'h15 8'h16 8'h17 8'h18 8'h19 8'h1a 8'h1b 8'h1c 8'h1d 8'h1e 8'h1f 8'h20 8'h21 8'h22 8'h23 8'h24 8'h25 8'h26 8'h27 8'h28 8'h29 8'h2a 8'h2b 8'h2c 8'h2d 8'h2e 8'h2f 8'h30 8'h31 8'h32 8'h33 8'h34 8'h35 8'h36 8'h37 8'h38 8'h39 8'h3a 8'h3b 8'h3c 8'h3d 8'h3e 8'h3f 8'h40 8'h41 8'h42 8'h43 8'h7c 8'h75 8'h46 8'hc7 8'h5d 8'h4d 8'h4a 8'h4b 8'h4c 8'h4d 8'h4e 8'h4f 8'h50 8'hd7 8'hd7 8'h53 8'h54 8'h55 8'h56 8'h57 8'h58 8'h59 8'h5a 8'h5b 8'h5c 8'h5d 8'h5e 8'h5f 8'h60 8'h61 8'h62 8'h63 8'h64 8'h65 8'h66 8'h67 8'h68 8'h69 8'h6a 8'h6b 8'h6c 8'h6d 8'h6e 8'h6f 8'h70 8'h71 8'h72 8'hf3 8'h74 8'h75 8'h77 8'h77 8'h78 8'h79 8'h7a 8'h7b 8'h7c 8'hfd 8'h7e 8'h7f 8'h00 8'h04 16'h0074 8'h01 16'h0004 8'h03 8'h00 8'h06 8'h00 16'h0074 8'h01 16'h0004 8'h00 8'h00 8'h0f 8'h00 16'h0074 8'h01 16'h0004 8'h00 8'h00 8'h0f 8'h00 diff --git a/tb/shinTest/testcase_result/base_tc08_result.log b/tb/shinTest/testcase_result/base_tc08_result.log index 9422fb7..97137a6 100644 --- a/tb/shinTest/testcase_result/base_tc08_result.log +++ b/tb/shinTest/testcase_result/base_tc08_result.log @@ -3,17 +3,19 @@ 16'h0040 8'h00 16'h0004 8'h01 8'h00 8'h66 8'h79 16'h0074 8'h01 16'h0004 8'h00 8'h00 8'h00 8'h80 16'h0074 8'h01 16'h0004 8'h00 8'h00 8'h00 8'h80 -16'h0040 8'h01 16'h0004 8'h00 8'h00 8'h00 8'h00 -16'h0040 8'h01 16'h0004 8'h00 8'h00 8'h00 8'h00 +16'h0070 8'h01 16'h0004 8'h00 8'h00 8'h00 8'he0 +16'h0070 8'h01 16'h0004 8'h00 8'h00 8'h00 8'he0 16'h0000 8'h00 16'h0001 8'h01 16'h0000 8'h00 16'h0001 8'h02 16'h0302 8'h00 16'h0002 8'h8c 8'h00 16'h0306 8'h00 16'h0002 8'h8c 8'h00 16'h1000 8'h00 16'h008c 8'h08 8'h80 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'hd0 8'h80 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 16'h0020 8'h00 16'h0001 8'h01 -16'h0800 8'h01 16'h008c 8'h08 8'h80 8'h00 8'h01 8'h00 8'h00 8'h00 8'h00 8'hd0 8'h80 8'h02 8'h01 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h55 8'h00 8'h01 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h5d 8'hc0 8'h00 8'h80 8'h15 8'h05 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h87 8'h87 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'hf0 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h81 8'h00 8'h00 8'h00 8'h01 +16'h0800 8'h01 16'h008c 8'h08 8'h80 8'h00 8'h01 8'h00 8'h00 8'h00 8'h00 8'hd0 8'h80 8'h02 8'h01 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h55 8'h00 8'h01 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h3c 8'h31 8'h00 8'h80 8'h15 8'h05 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h87 8'h87 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'hf0 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h00 8'h81 8'h00 8'h00 8'h00 8'h01 16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff 16'h0078 8'h00 16'h0004 8'hff 8'hff 8'hff 8'hff +16'h007c 8'h00 16'h0002 8'h00 8'h81 +16'h007c 8'h00 16'h0002 8'h00 8'h81 16'h00c0 8'h01 16'h0004 8'h08 8'h00 8'h02 8'h00 16'h00c0 8'h01 16'h0004 8'h00 8'h00 8'h00 8'h00 16'h00c0 8'h01 16'h0004 8'h08 8'h00 8'h04 8'h00 From 4b90a2c9bd086d9702f284d72af21492547cdb52 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 26 Aug 2025 17:52:23 +0800 Subject: [PATCH 09/11] =?UTF-8?q?CDR=E6=8B=89=E5=88=B0=E9=A1=B6=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MstSlvSwitch.scala | 96 +++++++++++++------ src/main/scala/backBoard/shin/ShinTop.scala | 83 +++------------- 2 files changed, 78 insertions(+), 101 deletions(-) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 54041bf..8bdfac4 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -3,16 +3,12 @@ package BACK import chisel3._ import chisel3.util._ - -class MstSlvSwitchIO extends Bundle{ - +class TopBase_IO_Bundle extends Bundle{ val dDatIn = Input(Bool()) val dDatOut = Output(Bool()) val uDatIn = Input(Bool()) val uDatOut = Output(Bool()) - val multiCLK = Input(Vec(16, Bool())) - val iqspi = new QSPIInterfaceIO val ospi = new SSPIInterfaceIO val oqspi = new QSPIInterfaceIO @@ -40,6 +36,17 @@ class MstSlvSwitchIO extends Bundle{ +class MstSlvSwitchIO extends TopBase_IO_Bundle{ + + val downCDROut = Flipped(new CDROutIO) + val upCDROut = Flipped(new CDROutIO) + val downCDRIn = Flipped(new CDRInIO) + val upCDRIn = Flipped(new CDRInIO) + +} + + + @@ -61,10 +68,10 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ interface.io.uniCode := io.uniCode interface.io.hwSerial := io.hwSerial - interface.io.intTransEnd(0) := downCDRIn.io.axis.fire & downCDRIn.io.axis.bits.tlast - interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast - interface.io.intTransEnd(2) := upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast - interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast + interface.io.intTransEnd(0) := io.downCDRIn.axis.fire & io.downCDRIn.axis.bits.tlast + interface.io.intTransEnd(1) := io.downCDROut.axis.fire & io.downCDROut.axis.bits.tlast + interface.io.intTransEnd(2) := io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast + interface.io.intTransEnd(3) := io.upCDROut.axis.fire & io.upCDROut.axis.bits.tlast io.isSoftReset := interface.io.isSoftReset io.interrupt := interface.io.interrupt @@ -203,24 +210,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ slaveParser.io.sram_r(3).datar := 0.U masterParser.io.sram_r.datar := 0.U - downCDRIn.io.axis.ready := false.B + io.downCDRIn.axis.ready := false.B slaveParser.io.downIn.valid := false.B slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) slaveParser.io.downOut.ready := false.B masterParser.io.downOut.ready := false.B - downCDROut.io.axis.valid := false.B - downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + io.downCDROut.axis.valid := false.B + io.downCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - upCDRIn.io.axis.ready := false.B + io.upCDRIn.axis.ready := false.B slaveParser.io.upIn.valid := false.B slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) masterParser.io.upIn.valid := false.B masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) slaveParser.io.upOut.ready := false.B - upCDROut.io.axis.valid := false.B - upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + io.upCDROut.axis.valid := false.B + io.upCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) interface.io.mstDeltaTime := 0.U @@ -252,8 +259,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === true.B ){ - masterParser.io.downOut <> downCDROut.io.axis - masterParser.io.upIn <> upCDRIn.io.axis + masterParser.io.downOut <> io.downCDROut.axis + masterParser.io.upIn <> io.upCDRIn.axis } when( interface.io.cReg.modeSel === true.B ){ @@ -312,10 +319,10 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === false.B ){ - slaveParser.io.downIn <> downCDRIn.io.axis - downCDROut.io.axis <> slaveParser.io.downOut - slaveParser.io.upIn <> upCDRIn.io.axis - upCDROut.io.axis <> slaveParser.io.upOut + slaveParser.io.downIn <> io.downCDRIn.axis + io.downCDROut.axis <> slaveParser.io.downOut + slaveParser.io.upIn <> io.upCDRIn.axis + io.upCDROut.axis <> slaveParser.io.upOut } slaveParser.io.cReg := interface.io.cReg @@ -366,10 +373,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - downCDRIn.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDRIn.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) - downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) - upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) + io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) ) + io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) ) interface.io.lvds <> slaveParser.io.lvds @@ -385,7 +392,7 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => } -trait MstSlvSwitchDog{ this: MstSlvSwitchBase => +trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => //看门狗1~16，SM监控 val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) } @@ -422,11 +429,11 @@ trait MstSlvSwitchDog{ this: MstSlvSwitchBase => val wdtRec2RtnCnt = Reg(UInt(32.W)) when( - (upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast) | + (io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) | ~interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := false.B - } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ + } .elsewhen( ~isWdtRec2RtnEnable & io.downCDROut.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := true.B } @@ -447,7 +454,7 @@ trait MstSlvSwitchDog{ this: MstSlvSwitchBase => wdtRec2RecCnt := wdtRec2RecCnt + 1.U } .elsewhen( ~interface.io.cReg.wdtEnable.extract(17) || - downCDRIn.io.axis.fire || + io.downCDRIn.axis.fire || (wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17)) ){ wdtRec2RecCnt := 0.U @@ -466,6 +473,37 @@ with MstSlvSwitchWatchDog{ + when( interface.io.cReg.modeSel === false.B ){ //slave + when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 + io.downCDRIn.serDat := false.B + io.upCDRIn.serDat := false.B + when( slaveParser.io.isLoop ){ //回环 + io.dDatOut := false.B + io.uDatOut := io.dDatIn + } .otherwise{ //非回环 + io.dDatOut := io.dDatIn + io.uDatOut := io.uDatIn + } + } .otherwise{ //无硬件错误 + when( slaveParser.io.isLoop ){ //回环 + io.downCDRIn.serDat := io.dDatIn + io.upCDRIn.serDat := io.downCDROut.serDat + io.dDatOut := false.B + io.uDatOut := io.upCDROut.serDat + } .otherwise{ //非回环 + io.downCDRIn.serDat := io.dDatIn + io.upCDRIn.serDat := io.uDatIn + io.dDatOut := io.downCDROut.serDat + io.uDatOut := io.upCDROut.serDat + } + } + } .otherwise{ //master + io.downCDRIn.serDat := false.B + io.upCDRIn.serDat := io.uDatIn + io.dDatOut := io.downCDROut.serDat + io.uDatOut := false.B + } + diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index e9b548f..9c634c5 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -3,94 +3,33 @@ package BACK import chisel3._ import chisel3.util._ +import chisel3.experimental.dataview._ - -class ShinTopIO extends Bundle{ - - val dDatIn = Input(Bool()) - val dDatOut = Output(Bool()) - val uDatIn = Input(Bool()) - val uDatOut = Output(Bool()) - +class ShinTopIO extends TopBase_IO_Bundle{ val multiCLK = Input(Vec(16, Bool())) - - val iqspi = new QSPIInterfaceIO - val ospi = new SSPIInterfaceIO - val oqspi = new QSPIInterfaceIO - - val iSync = Output(Vec(4, Bool())) - - val isSoftReset = Output(Bool()) - - val interrupt = Output(Bool()) - - val latchPin = Input(Vec(2, Bool())) - val hwSerial = Input(UInt(48.W)) - val uniCode = Input(UInt(64.W)) - - val pllCtrl = Output(UInt(32.W)) - val xtal = Output(UInt(12.W)) - val anamuxSel = Output(UInt(5.W)) - val ldo2p5 = Output(UInt(8.W)) - val ldo1p1 = Output(UInt(8.W)) - val refTop = Output(UInt(3.W)) - val bias = Output(UInt(2.W)) - - val spiSel = Output(UInt(2.W)) } class ShinTop extends Module with RequireAsyncReset{ + val io: ShinTopIO = IO(new ShinTopIO) - - - downCDRIn.multiCLK := io.multiCLK - upCDRIn.multiCLK := io.multiCLK - - + val mstSlvSwitch = Module(new MstSlvSwitch) val downCDROut = Module(new CDROut) val upCDROut = Module(new CDROut) val downCDRIn = Module(new MPCDRIn) val upCDRIn = Module(new MPCDRIn) + downCDRIn.multiCLK := io.multiCLK + upCDRIn.multiCLK := io.multiCLK + downCDROut.io <> mstSlvSwitch.io.downCDROut + upCDROut.io <> mstSlvSwitch.io.upCDROut + downCDRIn.io <> mstSlvSwitch.io.downCDRIn + upCDRIn.io <> mstSlvSwitch.io.upCDRIn - - when( interface.io.cReg.modeSel === false.B ){ //slave - when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 - downCDRIn.io.serDat := false.B - upCDRIn.io.serDat := false.B - when( slaveParser.io.isLoop ){ //回环 - io.dDatOut := false.B - io.uDatOut := io.dDatIn - } .otherwise{ //非回环 - io.dDatOut := io.dDatIn - io.uDatOut := io.uDatIn - } - } .otherwise{ //无硬件错误 - when( slaveParser.io.isLoop ){ //回环 - downCDRIn.io.serDat := io.dDatIn - upCDRIn.io.serDat := downCDROut.io.serDat - io.dDatOut := false.B - io.uDatOut := upCDROut.io.serDat - } .otherwise{ //非回环 - downCDRIn.io.serDat := io.dDatIn - upCDRIn.io.serDat := io.uDatIn - io.dDatOut := downCDROut.io.serDat - io.uDatOut := upCDROut.io.serDat - } - } - } .otherwise{ //master - downCDRIn.io.serDat := false.B - upCDRIn.io.serDat := io.uDatIn - io.dDatOut := downCDROut.io.serDat - io.uDatOut := false.B - } - - - + io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle) From c69acb4bf030ca764d429225f2f449308bf8b593 Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 26 Aug 2025 20:35:21 +0800 Subject: [PATCH 10/11] =?UTF-8?q?sync=E4=B8=8D=E8=83=BD=E5=B7=A5=E4=BD=9C,?= =?UTF-8?q?=E5=B7=B2=E7=A1=AE=E8=AE=A4,=E9=9C=80=E8=A6=81=E6=A3=80?= =?UTF-8?q?=E6=9F=A5=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 8 ++++---- tb/shinTest/testcase/sync.py | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index c80177b..ffe78e6 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -39,16 +39,16 @@ if __name__ == '__main__': #add_tc_2_runlist(base.tc23()) #add_tc_2_runlist(base.tc24()) #add_tc_2_runlist(base.tc25()) - add_tc_2_runlist(base.tc26()) + #add_tc_2_runlist(base.tc26()) #add_tc_2_runlist(broadcast.tc1()) #add_tc_2_runlist(broadcast.tc2()) #add_tc_2_runlist(broadcast.tc3()) - #add_tc_2_runlist(sync.tc1()) - #add_tc_2_runlist(sync.tc2()) - #add_tc_2_runlist(sync.tc3()) + add_tc_2_runlist(sync.tc1()) + add_tc_2_runlist(sync.tc2()) + add_tc_2_runlist(sync.tc3()) #add_tc_2_runlist(sync.tc4()) #add_tc_2_runlist(sync.tc5()) #add_tc_2_runlist(sync.tc6()) diff --git a/tb/shinTest/testcase/sync.py b/tb/shinTest/testcase/sync.py index 13d90b2..14fa72d 100644 --- a/tb/shinTest/testcase/sync.py +++ b/tb/shinTest/testcase/sync.py @@ -254,7 +254,7 @@ def tc3(): genPkt.addBeforeExc(genEnableInsertTimeCode(0xa, 1, 1) + '''spi_trans( (16'h0100), (`SPI_READ), (8), (`IF_IDX(0)));\n''' + '''_temp_time = rxBuf[3] + (rxBuf[4] << 8) + (rxBuf[5] << 16) + (rxBuf[6] << 24) + (rxBuf[7] << 32) + (rxBuf[8] << 40) + (rxBuf[9] << 48) + (rxBuf[10] << 56);\n''' - + '''_temp_time = _temp_time + 32'h3000;\n\n''') + + '''_temp_time = _temp_time + 32'h4000;\n\n''') genPkt.addSubPkt(0x0, 0, 0x0, 0xc, 12, b'\0'*12) #subPkt参数：索引、索引类型、地址、命令、长度、数据 @@ -333,7 +333,7 @@ def tc3(): +genWriteTransPktCode(gen_file_def_ap, sm_idx) +genTrgTransPktCode(gen_file_def_ap, sm_idx) +genReadAckPktCode(gen_file_def_ap, sm_idx) - +"#500000" + +"#2000000\n" +genMessageCode("--读取中断") +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(1, 0x74, False, 4) From 4e2e3f6ca46f065adfa7a3badd08a06069bacd2f Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 27 Aug 2025 09:42:01 +0800 Subject: [PATCH 11/11] =?UTF-8?q?=E4=BF=AE=E5=A4=8Dsync=E7=9A=8464?= =?UTF-8?q?=E4=BD=8D=E5=8A=A0=E6=B3=95=E5=99=A8=E8=BE=93=E5=85=A5=E4=BD=8D?= =?UTF-8?q?=E5=AE=BD=E8=BD=AC=E6=8D=A2=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 5d09eb4..6de0889 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -818,6 +818,7 @@ trait SlaveParserSync{ this: SlaveParserBase => val addr64_res = addr64_op1 + addr64_op2 val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B})) + dontTouch(addrConflict) assert( PopCount(addrConflict) <= 1.U ) @@ -933,8 +934,8 @@ trait SlaveParserSync{ this: SlaveParserBase => when( RegNext(isSync) & ~isSync ){ // deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 - addr64_op1 := mstDeltaTimeStamp //组合逻辑 - addr64_op2 := subOp2(slvDeltaTimeStamp) //组合逻辑 + addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑 + addr64_op2 := subOp2( Cat( Fill(32, slvDeltaTimeStamp(31)), slvDeltaTimeStamp) ) //组合逻辑 addrConflict(2) := true.B //组合逻辑 deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑