From bcc6528813b5d83f43fccbe5fccf71ef6c354008 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 23 May 2025 15:20:01 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8Dlvds=E6=96=B9=E5=90=91?=
 =?UTF-8?q?=E7=9A=84=E8=AF=BB?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index b7bacb5..5964751 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -604,7 +604,7 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
   
-  io.lvds.datar := AcquireReg(addr = io.lvds.addrr)
+  io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
 
   when( io.lvds.isEnW & isSlvMode ){