diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index b7bacb5..5964751 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -604,7 +604,7 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
   
-  io.lvds.datar := AcquireReg(addr = io.lvds.addrr)
+  io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
 
   when( io.lvds.isEnW & isSlvMode ){