diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
index 22c6208..701c041 100644
--- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala
+++ b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
@@ -429,9 +429,9 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
   
   isTLReadStatus         := io.cmd.fire & io.cmd.bits.inst.funct === 26.U
   val isTLReadInterrupt   = io.cmd.fire & io.cmd.bits.inst.funct === 27.U & io.cmd.bits.inst.xd
-  val isTLClearInterrupt  = io.cmd.fire & io.cmd.bits.inst.funct === 28.U & io.cmd.bits.inst.xs1
-  val isTLWriteIntMask    = io.cmd.fire & io.cmd.bits.inst.funct === 29.U
-  isReadIsLast           := io.cmd.fire & io.cmd.bits.inst.funct === 30.U
+  val isTLClearInterrupt  = io.cmd.fire & io.cmd.bits.inst.funct === 27.U & io.cmd.bits.inst.xs1
+  val isTLWriteIntMask    = io.cmd.fire & io.cmd.bits.inst.funct === 28.U
+  isReadIsLast           := io.cmd.fire & io.cmd.bits.inst.funct === 29.U