sync

src/main/scala/backBoard/BackBoardMst.scala

@@ -5,24 +5,83 @@ import chisel3.util._
 
 
 class BackBoardMstIO extends Bundle{
-  val downStreamReqDat  = Input( Bool() )
+  val FSMC = new FSMC_Port_Bundle
-  val downStreamRespdat = Output(Bool())
 
-  val CS   = Input(Bool())
+  val reset     = Input(Bool())
-  val MISO = Output(Bool())
+  val oser_pclk = Input(Bool())
-  val MOSI = Input(Bool())
+  val oser_fclk = Input(Bool())
-  val SCK  = Input(Bool())
+  val ides_pclk = Input(Bool())
-
+  val ides_fclk = Input(Bool())
-  val interrupt = Output(Bool())
-
-  val clk4            = Input( Bool() )
 
+  val lvds_down_dout = Output(Bool())
+  val lvds_up_din    = Input(Bool())
 }
 
 
-class BackBoardMst extends Module{
+class BackBoardMst extends RawModule{
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
 
+  val fsmcSlv = Module(new FSMCSlv)
+
+  fsmcSlv.io.FSMC <> io.FSMC
+
+
+
+
+
+
+  val lvdsMst = Module(new Lvds_Bus_Master)
+  lvdsMst.io.rst_n     := ~io.reset
+  lvdsMst.io.oser_pclk := io.oser_pclk
+  lvdsMst.io.oser_fclk := io.oser_fclk
+  lvdsMst.io.ides_pclk := io.ides_pclk
+  lvdsMst.io.ides_fclk := io.ides_fclk
   
+  io.lvds_down_dout      := lvdsMst.io.lvds_down_dout
+  lvdsMst.io.lvds_up_din := io.lvds_up_din
+    
+
+
+
+  lvdsMst.io.frame_info_update_en = Input(Bool())
+  lvdsMst.io.slave_type_num       = Input(UInt(8.W))
+  lvdsMst.io.slave_data_length    = Input(UInt(8.W))
+  lvdsMst.io.tx_start             = Input(Bool())
+  lvdsMst.io.tx_data_in           = Input(UInt(8.W))
+  lvdsMst.io.tx_data_ready        = Output(Bool())
+  lvdsMst.io.downstream_busy      = Output(Bool())
+  lvdsMst.io.rx_data_out          = Output(UInt(8.W))
+  lvdsMst.io.rx_data_valid        = Output(Bool())
+
+  lvdsMst.io.upstream_crc_valid     = Output(Bool())
+  lvdsMst.io.upstream_crc_err       = Output(Bool())
+  lvdsMst.io.upstream_crc_err_count = Output(UInt(8.W))
+  lvdsMst.io.upstream_cdr_err       = Output(Bool())
+
+  
+
+
+  fsmcSlv.io.CDRIn  = Flipped(Valid(new CDRData))
+  fsmcSlv.io.CDROut = Valid(new CDRData)
+
+
+
+  val stateNxt = Wire( UInt( 2.W ) )
+  val stateCur = RegNext( stateNxt, 0.U )
+
+  when( stateCur === 0.U ){
+    stateNxt := 0.U
+    when(  )
+  } .elsewhen( stateCur === 1.U ){
+    stateNxt := 1.U
+  } .elsewhen( stateCur === 2.U ){
+    stateNxt := 2.U
+  } .elsewhen( stateCur === 3.U ){
+    stateNxt := 3.U
+  }
+
+
+
+
 }