From bbabcb85497ec07e19a5b203b6039f5a10aa5b86 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 21 Mar 2024 19:08:34 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BD=BF=E7=94=A8=E6=B5=8B=E8=AF=95IO=E4=B8=8A?=
 =?UTF-8?q?=E8=B7=B3=E6=B2=BF=E6=9B=BF=E4=BB=A3=E5=86=99=E6=9C=89=E6=95=88?=
 =?UTF-8?q?=E7=9A=84ctrlTransmit=20=E5=86=99=E5=85=A5=EF=BC=8C=E6=95=88?=
 =?UTF-8?q?=E6=9E=9C=E5=BE=88=E5=A5=BD=EF=BC=8C=E5=8F=AF=E4=BB=A5=E8=AE=A4?=
 =?UTF-8?q?=E4=B8=BA=EF=BC=8C=E5=BD=93=E5=89=8D=E6=9C=89=E9=97=AE=E9=A2=98?=
 =?UTF-8?q?=E7=9A=84=E6=98=AF=E5=AF=84=E5=AD=98=E5=99=A8=E5=86=99=E5=85=A5?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/BackBoardMst.scala | 9 ++++++++-
 src/main/verilog/backBoardMstTop.v          | 6 ++++--
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 4ee40ff..a331cfe 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -32,6 +32,8 @@ val reset_calib = Input(Bool())
 
   val interrupt = Output(Bool())
 
+  val testIO = Input(Bool())
+
 }
 
 class BackBoardMstBase extends Module{ //10M
@@ -170,6 +172,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   }
 
   //10M
+  when(~RegNext( io.testIO, false.B ) & io.testIO){
+    ctrlTransmit := true.B
+  }
+
+
   when( isAckReady ){
     isAckReady := false.B
   }
@@ -191,7 +198,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
     when( wrRegAddr === 1.U ){
-      ctrlTransmit := wrRegData.extract(5)
+      // ctrlTransmit := wrRegData.extract(5)
 
       ctrlSynch    := wrRegData.extract(1)
 
diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v
index 68a5487..4a80b31 100644
--- a/src/main/verilog/backBoardMstTop.v
+++ b/src/main/verilog/backBoardMstTop.v
@@ -20,7 +20,8 @@ module master_top(
   input         io_FSMC_wrn,
   input         io_FSMC_advn,
 
-  output        interrupt
+  output        interrupt,
+  input testIO
 );
 
 wire [15:0] io_FSMC_ADIn;
@@ -154,7 +155,8 @@ BackBoardMst i_BackBoardMst(
     .io_lvds_down_dout(lvds_down_dout),
     .io_lvds_up_din(lvds_up_din),
 
-    .io_interrupt(interrupt)
+    .io_interrupt(interrupt),
+    .io_testIO(testIO)
 );