diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 4ee40ff..a331cfe 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -32,6 +32,8 @@ val reset_calib = Input(Bool())
 
   val interrupt = Output(Bool())
 
+  val testIO = Input(Bool())
+
 }
 
 class BackBoardMstBase extends Module{ //10M
@@ -170,6 +172,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   }
 
   //10M
+  when(~RegNext( io.testIO, false.B ) & io.testIO){
+    ctrlTransmit := true.B
+  }
+
+
   when( isAckReady ){
     isAckReady := false.B
   }
@@ -191,7 +198,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
     when( wrRegAddr === 1.U ){
-      ctrlTransmit := wrRegData.extract(5)
+      // ctrlTransmit := wrRegData.extract(5)
 
       ctrlSynch    := wrRegData.extract(1)
 
diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v
index 68a5487..4a80b31 100644
--- a/src/main/verilog/backBoardMstTop.v
+++ b/src/main/verilog/backBoardMstTop.v
@@ -20,7 +20,8 @@ module master_top(
   input         io_FSMC_wrn,
   input         io_FSMC_advn,
 
-  output        interrupt
+  output        interrupt,
+  input testIO
 );
 
 wire [15:0] io_FSMC_ADIn;
@@ -154,7 +155,8 @@ BackBoardMst i_BackBoardMst(
     .io_lvds_down_dout(lvds_down_dout),
     .io_lvds_up_din(lvds_up_din),
 
-    .io_interrupt(interrupt)
+    .io_interrupt(interrupt),
+    .io_testIO(testIO)
 );