From bb35dffb84dbed7a79758b77d303c3e18fa80762 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 12 Oct 2023 18:37:12 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9C=AA=E5=AE=8C=E6=88=90tx=E6=8B=86=E8=A7=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/TxBuff.scala | 40 ++++++++++++++++++ src/main/scala/mac/MAC.scala | 1 - src/main/scala/mac/MacTilelink.scala | 63 ++++++++-------------------- 3 files changed, 58 insertions(+), 46 deletions(-) create mode 100644 src/main/scala/Switch/TxBuff.scala diff --git a/src/main/scala/Switch/TxBuff.scala b/src/main/scala/Switch/TxBuff.scala new file mode 100644 index 0000000..59e4c05 --- /dev/null +++ b/src/main/scala/Switch/TxBuff.scala @@ -0,0 +1,40 @@ +package MAC + +import chisel3._ +import chisel3.util._ + + +class Transmit_Enq_Ctrl_Bundle extends Bundle{ + +} + +class Transmit_Deq_Ctrl_Bundle extends Bundle{ + +} + +class Transmit_Enq_Bundle extends Bundle{ + val data = Decoupled(UInt(32.W)) + val ctrl = Decoupled(new RevBuff_Enq_Ctrl_Bundle) +} + + +class Transmit_Deq_Bundle extends Bundle{ + val data = Decoupled(UInt(32.W)) + val ctrl = Decoupled(new RevBuff_Deq_Ctrl_Bundle) +} + + +class TxBuffIO extends Bundle{ + val enq = Flipped(new Transmit_Enq_Bundle) + val deq = new Transmit_Deq_Bundle +} + + +class TxBuff extends Module{ + val io: TxBuffIO = IO(new TxBuffIO) + + + + + +} diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala index 6c4511e..f3a4d61 100644 --- a/src/main/scala/mac/MAC.scala +++ b/src/main/scala/mac/MAC.scala @@ -714,7 +714,6 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul wishbone.io.r_TxEn := r_TxEn wishbone.io.r_RxEn := r_RxEn - wishbone.io.r_TxBDNum := r_TxBDNum TxB_IRQ := wishbone.io.TxB_IRQ TxE_IRQ := wishbone.io.TxE_IRQ RxB_IRQ := false.B diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index 18cfda9..2535756 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -46,31 +46,24 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod //Register val r_TxEn = Input(Bool()) // Transmit enable - val r_RxEn = Input(Bool()) // Receive enable - val r_TxBDNum = Input(UInt(8.W)) // Receive buffer descriptor number // Interrupts val TxB_IRQ = Output(Bool()) val TxE_IRQ = Output(Bool()) - // val Busy_IRQ = Output(Bool()) - - - val BlockingTxStatusWrite = Output(Bool()) val ReadTxDataFromFifo_sync = Input(Bool()) val TxData_wb = Output(UInt(32.W)) + val TxValidBytesLatched = Output(UInt(2.W)) val TxStartFrm_wb = Output(Bool()) val TxStartFrm_syncb = Input(Bool()) + val TxEndFrm_wb = Output(Bool()) val TxUnderRun_wb = Output(Bool()) - - val TxEndFrm_wb = Output(Bool()) - val TxRetrySync = Input(Bool()) val TxAbortSync = Input(Bool()) // Transmit packet abort val TxDoneSync = Input(Bool()) // Transmission ended @@ -79,22 +72,22 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod - + val r_RxEn = Input(Bool()) // Receive enable val RxDataLatched2_rxclk = Input(UInt(32.W)) val WriteRxDataToFifoSync = Input(Bool()) - val RxAbortSync = Input(Bool()) - val LatchedRxLength_rxclk = Input(UInt(16.W)) val RxStatusInLatched_rxclk = Input(UInt(9.W)) - val ShiftEndedSync = Input(Bool()) - val RxReady = Output(Bool()) - val rxDeq = new RevBuff_Enq_Bundle + + + val txEnq = Flipped(new TxBuff_Deq_Bundle) + + } @@ -102,12 +95,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val io = IO(new MacTileLinkIO) - - - - - - val ShiftEndedSyncPluse = io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B) val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B) val WriteRxDataToFifoSyncPluse = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B) @@ -162,12 +149,15 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod + val TxStartFrm_wb = RegInit(false.B); io.TxStartFrm_wb := TxStartFrm_wb - - - + when( io.txEnq.ctrl.fire ){ + TxStartFrm_wb := true.B + } .elsewhen(io.TxStartFrm_syncb){ + TxStartFrm_wb := false.B + } @@ -180,10 +170,13 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val TxRetryPacket = RegInit(false.B) val TxRetryPacket_NotCleared = RegInit(false.B) + val TxDonePacket = RegInit(false.B) val TxDonePacket_NotCleared = RegInit(false.B) + val TxAbortPacket = RegInit(false.B) val TxAbortPacket_NotCleared = RegInit(false.B) + val TxBDReady = RegInit(false.B) val TxBDAddress = RegInit(0.U(7.W)) //[7:1] @@ -199,7 +192,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val TxStatusWrite = Wire(Bool()) val TxLength = RegInit(0.U(16.W)) val TxStatus = RegInit(0.U(4.W)) //[14:11] - val TxStartFrm_wb = RegInit(false.B); io.TxStartFrm_wb := TxStartFrm_wb + val TxRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B) val TxDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B) val TxAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B) @@ -243,11 +236,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod - - - - val StartOccured = RegInit(false.B) - val BlockReadTxDataFromMemory = RegInit(false.B) @@ -527,21 +515,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod - // Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk - when(TxBDReady & ~StartOccured & (tx_fifo.io.full | TxLength === 0.U)){ - TxStartFrm_wb := true.B - } .elsewhen(io.TxStartFrm_syncb){ - TxStartFrm_wb := false.B - } - // StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked. - when(TxStartFrm_wb){ - StartOccured := true.B - } .elsewhen(ResetTxBDReady){ - StartOccured := false.B - } - // TxEndFrm_wb: indicator of the end of frame when((TxLength === 0.U) & tx_fifo.io.almost_empty & io.TxUsedData){ @@ -766,8 +741,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod val tlMstDReady = RegInit(true.B) - dontTouch(tlMstDReady) - dontTouch(tlMstAValid_dbg) io.tlMst.D.ready := tlMstDReady