同步逻辑扩展delta位宽，使用分时共享64位加法器

src/main/scala/backBoard/shin/Interface.scala

@@ -138,7 +138,7 @@ class SlaveRegisterBundle extends Bundle{
 
 
   val slvDeltaTime  = UInt(32.W) //从站时间戳差值
-  val deltaFinal    = UInt(32.W) //当前时间戳与主站时间差
+  val deltaFinal    = UInt(64.W) //当前时间戳与主站时间差
 
 
 
@@ -183,7 +183,7 @@ class InterfaceIO extends Bundle{
 
   val slvDeltaTime  = Input(UInt(32.W)) //从站时间戳差值
   val mstDeltaTime  = Input(UInt(32.W))
-  val deltaFinal = Input(UInt(32.W))
+  val deltaFinal = Input(UInt(64.W))
 
   val sync = Output(Vec(4, Bool()))
 
@@ -392,10 +392,10 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
         (addr === "h109".U & isSlvMode)  -> sReg.deltaFinal(15,8),
         (addr === "h10a".U & isSlvMode)  -> sReg.deltaFinal(23,16),
         (addr === "h10b".U & isSlvMode)  -> sReg.deltaFinal(31,24),
-        // (addr === "h10c".U & isSlvMode)  -> sReg.deltaFinal(39,32),
+        (addr === "h10c".U & isSlvMode)  -> sReg.deltaFinal(39,32),
-        // (addr === "h10d".U & isSlvMode)  -> sReg.deltaFinal(47,40),
+        (addr === "h10d".U & isSlvMode)  -> sReg.deltaFinal(47,40),
-        // (addr === "h10e".U & isSlvMode)  -> sReg.deltaFinal(55,48),
+        (addr === "h10e".U & isSlvMode)  -> sReg.deltaFinal(55,48),
-        // (addr === "h10f".U & isSlvMode)  -> sReg.deltaFinal(63,56),
+        (addr === "h10f".U & isSlvMode)  -> sReg.deltaFinal(63,56),
 
         //主站发送接收时间差
         (addr === "h110".U )  -> cReg.mstDeltaTime(7,0),  
@@ -963,7 +963,7 @@ trait InterfaceSync{ this: InterfaceBase =>
   sReg.deltaFinal := io.deltaFinal
   cReg.recoTimeStamp := 
     Mux(isMstMode, cReg.timeStamp,
-      RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
+      RegNext( cReg.timeStamp + sReg.deltaFinal )
     )
   sReg.slvDeltaTime := io.slvDeltaTime
   

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -66,7 +66,7 @@ class SlaveParserIO extends Bundle{
 
   val mstDeltaTimeStamp = Output(UInt(32.W))
   val slvDeltaTime = Output(UInt(32.W))
-  val deltaFinal        = Output(UInt(32.W))
+  val deltaFinal        = Output(UInt(64.W))
 
   val isLoop = Output(Bool())
 
@@ -812,6 +812,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
 
 trait SlaveParserSync{ this: SlaveParserBase =>
+  val addr64_op1 = WireDefault( 0.U(64.W) )
+  val addr64_op2 = WireDefault( 0.U(64.W) )
+  def subOp2(x:UInt) = ~x + 1.U 
+  val addr64_res = addr64_op1 + addr64_op2
+
+  val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B}))
+  assert( PopCount(addrConflict) <= 1.U )
+
 
   //下行接收
   when( downRecParser.io.subMsgTailReq.fire ){
@@ -837,9 +845,9 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
   val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
 
-  val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
+  val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量)
-  val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
+  val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量)
-  val deltaFinal = Reg(UInt(32.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
+  val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
 
 
   // val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
@@ -860,7 +868,12 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   //更新上行本地时间戳寄存器
   when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){
     upTimeStamp := io.cReg.timeStamp
-    slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
+
+    // slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
+    addr64_op1 := io.cReg.timeStamp //组合逻辑
+    addr64_op2 := subOp2(downTimeStamp) //组合逻辑
+    addrConflict(0) := true.B //组合逻辑
+    slvDeltaTimeStamp := addr64_res //时序逻辑
   }
 
   //下行接收
@@ -898,7 +911,13 @@ trait SlaveParserSync{ this: SlaveParserBase =>
     } .elsewhen( syncCnt === 7.U ){
       mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
     } .elsewhen( syncCnt === 8.U ){
-      mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
+      // mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
+
+      addr64_op1 := mstTimeStamp //组合逻辑
+      addr64_op2 := subOp2(downTimeStamp) //组合逻辑
+      addrConflict(1) := true.B //组合逻辑
+      mstSlvDeltaTimeStamp := addr64_res //时序逻辑
+
       mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
     } .elsewhen( syncCnt === 9.U ){
       mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
@@ -912,10 +931,19 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   }
 
   when( RegNext(isSync) & ~isSync ){
-    val deltaMstSlvDeltaTimeStamp_org = mstDeltaTimeStamp - slvDeltaTimeStamp
+    // deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
-    deltaMstSlvDeltaTimeStamp := Cat( deltaMstSlvDeltaTimeStamp_org.extract(deltaMstSlvDeltaTimeStamp_org.getWidth-1), deltaMstSlvDeltaTimeStamp_org(deltaMstSlvDeltaTimeStamp_org.getWidth-1, 1) ) //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
+
+    addr64_op1 := mstDeltaTimeStamp //组合逻辑
+    addr64_op2 := subOp2(slvDeltaTimeStamp) //组合逻辑
+    addrConflict(2) := true.B //组合逻辑
+    deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1))  //时序逻辑
+
   } .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
-    deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
+    // deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
+    addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
+    addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
+    addrConflict(3) := true.B //组合逻辑
+    deltaFinal := addr64_res  //时序逻辑
   }