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同步逻辑扩展delta位宽，使用分时共享64位加法器

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This commit is contained in:
Ruige Lee
2025-08-26 17:02:57 +08:00
parent ae99f5801d
commit b821571218
2 changed files with 44 additions and 16 deletions
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14
src/main/scala/backBoard/shin/Interface.scala
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@@ -138,7 +138,7 @@ class SlaveRegisterBundle extends Bundle{
val slvDeltaTime = UInt(32.W) //从站时间戳差值
val deltaFinal = UInt(32.W) //当前时间戳与主站时间差
val deltaFinal = UInt(64.W) //当前时间戳与主站时间差
@@ -183,7 +183,7 @@ class InterfaceIO extends Bundle{
val slvDeltaTime = Input(UInt(32.W)) //从站时间戳差值
val mstDeltaTime = Input(UInt(32.W))
val deltaFinal = Input(UInt(32.W))
val deltaFinal = Input(UInt(64.W))
val sync = Output(Vec(4, Bool()))
@@ -392,10 +392,10 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "h109".U & isSlvMode) -> sReg.deltaFinal(15,8),
(addr === "h10a".U & isSlvMode) -> sReg.deltaFinal(23,16),
(addr === "h10b".U & isSlvMode) -> sReg.deltaFinal(31,24),
// (addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32),
// (addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40),
// (addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48),
// (addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56),
(addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32),
(addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40),
(addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48),
(addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56),
//主站发送接收时间差
(addr === "h110".U ) -> cReg.mstDeltaTime(7,0),
@@ -963,7 +963,7 @@ trait InterfaceSync{ this: InterfaceBase =>
sReg.deltaFinal := io.deltaFinal
cReg.recoTimeStamp :=
Mux(isMstMode, cReg.timeStamp,
RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
RegNext( cReg.timeStamp + sReg.deltaFinal )
)
sReg.slvDeltaTime := io.slvDeltaTime