加入外置CRC32_32

src/main/scala/backBoard/ebus/TL2CDR.scala

@@ -235,10 +235,43 @@ trait TL2CDRIsLast{ this: TL2CDRBase =>
 
 }
 
+trait TL2CDRUserCRC{ this: TL2CDRBase =>
+  val isTLWriteTxFifo: Bool
+  val isTLReadRxFifo: Bool
+
+  val isTLReadTxCrc = io.tla.fire & io.tla.bits.address(5,0) === "h24".U & io.tla.bits.opcode === 4.U
+  val isTLReadRxCrc = io.tla.fire & io.tla.bits.address(5,0) === "h28".U & io.tla.bits.opcode === 4.U
+
+
+  val txCrc = Module(new crc32_32)
+  val rxCrc = Module(new crc32_32)
+
+  txCrc.io.enq.valid := isTLWriteTxFifo
+  txCrc.io.enq.bits  := io.tla.bits.data
+
+  rxCrc.io.enq.valid := isTLReadRxFifo
+  rxCrc.io.enq.bits  := rxFifo.io.deq.bits
+
+  txCrc.reset := reset.asBool | isTLWriteSoftReset
+  rxCrc.reset := reset.asBool | isTLWriteSoftReset
+
+
+
+}
+
+
+
+
+
+
+
+
+
 
 class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge)
 with TL2CDRTx with TL2CDRRx
 with TL2CDRIsLast
+with TL2CDRUserCRC
 {
 
   // val isWriteTransDir       = io.mem.fire & io.mem.addr(5,0) === "hc".U & io.mem.wstrb =/= 0.U
@@ -302,9 +335,12 @@ with TL2CDRIsLast
     rdata := rxFifo.io.deq.bits
   } .elsewhen(isReadIsLast){
     rdata := io.isLast
+  } .elsewhen(isTLReadTxCrc){
+    rdata := txCrc.io.crc
+  } .elsewhen(isTLReadRxCrc){
+    rdata := rxCrc.io.crc
   }
-
-
+  
 }