diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index ab14892..f62c652 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -44,32 +44,21 @@ class BackBoardMstBase extends Module{ //10M
   val mirrorUp   = Module(new MirrorSRAMUp())
   val mirrorReg  = Module(new MirrorSRAMDP())
 
-    mirrorReg.io.addrB  := DontCare
-    mirrorReg.io.datawB := DontCare
-    mirrorReg.io.enwB   := false.B
-    mirrorReg.io.enrB   := false.B
+  mirrorReg.io.addrB  := DontCare
+  mirrorReg.io.datawB := DontCare
+  mirrorReg.io.enwB   := false.B
+  mirrorReg.io.enrB   := false.B
 
-    assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) )
-    assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )
-
-  // val statusCDRErr  = RegInit( false.B )
-  // val statusCRCErr  = RegInit( false.B )
-  // val statusLinkErr = RegInit( false.B )
-  // val statusSynch   = RegInit( false.B )
-  // val statusInit    = RegInit( false.B )
+  assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) )
+  assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )
 
   val ctrlTransmit = RegInit( false.B )
   val ctrlSynch    = RegInit( false.B )
   val ctrlInit     = RegInit( false.B )
 
-  val ctrlFun = RegInit(0.U(8.W))
-
   val slvNum  = RegInit(0.U(6.W))
-  // val slvOffLine = RegInit(0.U(6.W))
-  // val linkNum = RegInit(0.U(7.W))
-  // val testReg = RegInit("haa55".U(16.W))
   val interrupt = RegInit(false.B); io.interrupt := interrupt
-  val slaveDataLength    = RegInit(((8/8)*32-1).U(8.W))
+  val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1
 
   lvdsMst.io.rst_n       := ~reset.asBool
   lvdsMst.io.reset_calib := io.reset_calib
@@ -106,15 +95,8 @@ class BackBoardMstBase extends Module{ //10M
 
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
-  val isReqValid       = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
-  val isAckReady       = RegInit(false.B)
-  val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
-  val wrRegData        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }  //100M
-
   withClockAndReset( io.ides_pclk.asClock, reset ){//100M
 
-
-
     io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn
 
     val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
@@ -122,9 +104,6 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     val isAccessSRAM = ~latchAddr.extract(10) 
     val isAccessReg  =  latchAddr.extract(10)
     val activeAddr   =  latchAddr(9,0)
-    // val regOut = Wire(UInt(16.W))
-
-
 
 
     mirrorDown.io.enw    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn
@@ -141,36 +120,6 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
     io.FSMC.ADOut   := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)
 
-    // regOut := Mux1H(Seq(
-    //   ( activeAddr === 0.U) -> 
-    //     Cat(
-    //       statusCDRErr ,
-    //       statusCRCErr ,
-    //       statusLinkErr,
-    //       statusSynch  ,
-    //       statusInit
-    //     ),
-    //   ( activeAddr === 1.U) -> ctrlFun,
-    //   ( activeAddr === 2.U) -> slvNum,
-    //   ( activeAddr === 3.U) -> slvOffLine,
-    //   ( activeAddr === 4.U) -> testReg,
-    //   ( activeAddr === 5.U) -> linkNum,
-    //   ( activeAddr === 6.U) -> slaveDataLength,
-    // ))
-
-
-
-    // when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){
-    //   isReqValid := true.B
-    //   wrRegAddr        := activeAddr
-    //   wrRegData        := io.FSMC.ADIn
-    // }
-
-    // when( isReqValid & isAckReady ){
-    //   isReqValid := false.B
-    // }
-
-
 
   }
 
@@ -194,48 +143,6 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     }
   }
 
-
-
-
-  // when( isAckReady ){
-  //   isAckReady := false.B
-  // }
-
-  // when( isReqValid ){
-  //   isAckReady := true.B
-
-  //   when( wrRegAddr === 0.U ){
-  //     when( wrRegData.extract(4) ){
-  //       statusCDRErr := false.B
-  //     }
-  //     when( wrRegData.extract(3) ){
-  //       statusCRCErr := false.B
-  //     }
-  //     when( wrRegData.extract(2) ){
-  //       statusLinkErr := false.B
-  //     }
-  //   }
-
-
-  //   when( wrRegAddr === 1.U ){
-  //     ctrlFun := wrRegData
-  //   }
-
-  //   when( wrRegAddr === 2.U ){
-  //     slvNum := wrRegData
-  //   }
-
-  //   when( wrRegAddr === 4.U ){
-  //     testReg := wrRegData
-  //   }
-
-  //   when( wrRegAddr === 6.U ){
-  //     slaveDataLength := wrRegData
-  //   }
-
-  // }
-
-
 }
 
 abstract class BackBoardMstLVDSBase extends BackBoardMstBase