From b271a1c85ffe45e5db2cc1173ee58731aa165a47 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 21 Mar 2024 15:17:37 +0800
Subject: [PATCH] =?UTF-8?q?=E7=94=A8=E5=BC=82=E6=AD=A5=E6=8F=A1=E6=89=8B?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 380e375..4ee40ff 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -94,7 +94,8 @@ class BackBoardMstBase extends Module{ //10M
 
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
-  val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
+  val isReqValid       = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
+  val isAckReady       = RegInit(false.B)
   val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
   val wrRegData        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }  //100M
 
@@ -155,10 +156,13 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
     when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){ //fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
-      isRegRefleshFlip := ~isRegRefleshFlip
+      isReqValid := true.B
       wrRegAddr        := activeAddr
       wrRegData        := io.FSMC.ADIn
+    }
 
+    when( isReqValid & isAckReady ){
+      isReqValid := false.B
     }
 
 
@@ -166,10 +170,12 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   }
 
   //10M
-  val isChkRegReflesh = RegInit(false.B)
+  when( isAckReady ){
+    isAckReady := false.B
+  }
 
-  when( isChkRegReflesh =/= isRegRefleshFlip ){
-    isChkRegReflesh := ~isChkRegReflesh
+  when( isReqValid ){
+    isAckReady := true.B
 
     when( wrRegAddr === 0.U ){
       when( wrRegData.extract(4) ){