diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 380e375..4ee40ff 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -94,7 +94,8 @@ class BackBoardMstBase extends Module{ //10M
 
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
-  val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
+  val isReqValid       = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
+  val isAckReady       = RegInit(false.B)
   val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
   val wrRegData        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }  //100M
 
@@ -155,10 +156,13 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
     when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){ //fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
-      isRegRefleshFlip := ~isRegRefleshFlip
+      isReqValid := true.B
       wrRegAddr        := activeAddr
       wrRegData        := io.FSMC.ADIn
+    }
 
+    when( isReqValid & isAckReady ){
+      isReqValid := false.B
     }
 
 
@@ -166,10 +170,12 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   }
 
   //10M
-  val isChkRegReflesh = RegInit(false.B)
+  when( isAckReady ){
+    isAckReady := false.B
+  }
 
-  when( isChkRegReflesh =/= isRegRefleshFlip ){
-    isChkRegReflesh := ~isChkRegReflesh
+  when( isReqValid ){
+    isAckReady := true.B
 
     when( wrRegAddr === 0.U ){
       when( wrRegData.extract(4) ){