DC 同步功能； 基于IO的下级从机热插入

Makefile

@@ -18,6 +18,7 @@ back:
 	# cp ./src/main/verilog/backBoardSlvTop.v ./generated/
 	cp ./src/main/verilog/oser_rst.v ./generated/
 	cp ./src/main/verilog/di16_top.v ./generated/
+	cp ./src/main/verilog/do16_top.v ./generated/
 	cp ./src/main/verilog/defineParam.v ./generated/
 
 

src/main/scala/backBoard/BackBoardSlv.scala

@@ -17,6 +17,11 @@ class BackBoardSlvIO extends Bundle{
   val lvds_down_dout = Output(Bool())
   val lvds_up_din    = Input(Bool())
   val lvds_up_dout   = Output(Bool())
+
+  val isOnline = Output(Bool())
+  val isLast   = Input(Bool())
+
+  val DCIn   = Input(Bool())
 }
 
 

src/main/scala/backBoard/LocalRegisters.scala

@@ -23,11 +23,13 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
   val statusPR   = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass )
   val statusER   = RegInit(false.B)
   val statusLE   = RegInit(false.B)
+  val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
+  val statusNone = ~io.isLast
 
 
 
   upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
-  upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) )
+  upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
 
   when( statusPage === 15.U ){
     upReg(2) := 0.U
@@ -63,6 +65,9 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
 
   val (usCounter, usTrigger) = Counter(Range(0, 10))
 
+  io.isOnline := false.B
+
+  val isUpdate = (statusSync & ~RegNext(io.DCIn) & io.DCIn) | (~statusSync)
 
 }
 
@@ -217,16 +222,16 @@ with BackBoardSlvIn16{
   inPin := in
 
 
-
-
   when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
     digitalFilter(0) := downRegTemp(4)
     digitalFilter(1) := downRegTemp(5)
   }
 
+  val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }
+
   when( statusPage === 0.U ){
-    upReg(2) := Cat( digitalIn(0).reverse  )
+    upReg(2) := digitalInSync(0)
-    upReg(3) := Cat( digitalIn(1).reverse  )
+    upReg(3) := digitalInSync(1)
     upReg(4) := digitalFilter(0)
     upReg(5) := digitalFilter(1)
   }
@@ -237,8 +242,7 @@ with BackBoardSlvIn16{
 
 trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
 
-  val outReg  = RegInit(0.U(16.W))
+  val outRegSync  = Wire(UInt(16.W))
-  val chsWire = Wire( Vec(16, UInt(2.W)) )
 
   val mthodReg = RegInit(0.U(16.W))
   val valueReg = RegInit(0.U(16.W))
@@ -246,7 +250,7 @@ trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
   val outPin = Wire(UInt(16.W))
 
   outPin := 
-    Mux(statusPR === 3.U, outReg, (mthodReg & valueReg) | (~mthodReg & outReg))
+    Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))
 
 }
 
@@ -256,25 +260,31 @@ with BackBoardSlvStatusPR
 with BackBoardSlvOut16{
   val out = IO(Output(UInt(16.W)))
   val flt = IO(Input(Vec(2, Bool())))
+  val outReg  = RegInit(0.U(16.W))
 
   when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
     outReg := Cat(downRegTemp(3), downRegTemp(2))
   }
-  when( isCrcPass & downRegTemp(0)(3,0) === 1.U ){
+  when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){
     mthodReg := Cat(downRegTemp(3), downRegTemp(2))
     valueReg := Cat(downRegTemp(5), downRegTemp(4))
   }
 
+  outRegSync := RegEnable( outReg, 0.U, isUpdate )
+
   when( statusPage === 0.U ){
-    upReg(4) := Cat( ( 3  to 0  by -1).map{ i => chsWire(i) } )
+    upReg(2) := outReg(7,0)
-    upReg(5) := Cat( ( 7  to 4  by -1).map{ i => chsWire(i) } )
+    upReg(3) := outReg(15,8)
-    upReg(6) := Cat( ( 11 to 8  by -1).map{ i => chsWire(i) } )
+    upReg(4) := Cat( ~flt(1), ~flt(0) )
-    upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
   }
 
-  for( i <- 0 until 8 ){
+  when( statusPage === 1.U ){
-    chsWire(i)   := Mux( flt(0) === true.B, "b00".U, "b01".U)
+    upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)
-    chsWire(8+i) := Mux( flt(1) === true.B, "b00".U, "b01".U)
+
+    upReg(4) := mthodReg(7,0)
+    upReg(5) := mthodReg(15,8)
+    upReg(6) := valueReg(7,0)
+    upReg(7) := valueReg(15,8)
   }
 
   out := outPin

src/main/verilog/di16_top.v

@@ -2,7 +2,6 @@
 
 module di16_top(
 
-  input resetn,
   input clock, 
      
   input  lvds_up_din_p,
@@ -15,11 +14,17 @@ module di16_top(
   output lvds_down_dout_p,
   output lvds_down_dout_n,
 
+  output isOnline,
+  input  isLast,
+  input  DCIn,
+
   output        LED_PR,
   input  [15:0] in
 
 );
 
+wire resetn = 1'b1;
+
 wire clk_400m;
 wire clk_400m_a;
 wire clk_100m_a;
@@ -139,6 +144,10 @@ DIn16 i_din16(
   .io_lvds_up_din(lvds_up_din),
   .io_lvds_up_dout(lvds_up_dout),
 
+  .io_isOnline(isOnline),
+  .io_isLast(isLast),
+  .io_DCIn(DCIn),
+
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),

src/main/verilog/do16_top.v

@@ -0,0 +1,171 @@
+
+
+module do16_top(
+
+
+  input clock, 
+     
+  input  lvds_up_din_p,
+  input  lvds_up_din_n, 
+  output lvds_up_dout_p,
+  output lvds_up_dout_n,  
+           
+  input  lvds_down_din_p,
+  input  lvds_down_din_n,  
+  output lvds_down_dout_p,
+  output lvds_down_dout_n,
+
+  output isOnline,
+  input  isLast,
+  input  DCIn,
+
+  output        LED_PR,
+  output [15:0] out,
+  input         flt_0,
+  input         flt_1
+
+);
+
+wire resetn = 1'b1;
+
+wire clk_400m;
+wire clk_400m_a;
+wire clk_100m_a;
+wire clk_50m_a;
+wire clk_10m_a;
+
+wire lock_o;
+wire reset_stop;
+wire reset_calib;
+
+reg rst_n;
+reg rstn_d;
+
+
+
+
+
+always@(posedge clk_10m_a) begin
+  rstn_d <= resetn;
+	rst_n <= rstn_d;
+end
+
+Gowin_PLLO Gowin_PLLO(
+  .lock(lock_o), 
+  .clkouta(clk_400m),
+  .clkin(clock)
+);
+
+
+
+TLVDS_OBUF lvds_downstream_out(
+  .O(lvds_down_dout_p),
+  .OB(lvds_down_dout_n),
+  .I(lvds_down_dout)
+);
+
+
+TLVDS_IBUF lvds_downstream_in(
+  .O(lvds_down_din),
+  .I(lvds_down_din_p),
+  .IB(lvds_down_din_n)
+);
+
+
+TLVDS_OBUF lvds_upstream_out(
+  .O(lvds_up_dout_p),
+  .OB(lvds_up_dout_n),
+  .I(lvds_up_dout)
+);
+
+
+TLVDS_IBUF lvds_upstream_in(
+  .O(lvds_up_din),
+  .I(lvds_up_din_p),
+  .IB(lvds_up_din_n)
+);
+
+
+DHCEN dhcen_inst2 (
+  .CLKIN(clk_400m),
+  .CE(reset_stop),
+  .CLKOUT(clk_400m_a)
+);
+
+
+//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
+oser_rst u_oser_rst(
+  .clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
+  .rst_n(rst_n),
+  .pll_lock(lock_o), // trigged by PLL Lock
+  .reset_stop(reset_stop), // for DHCEN CE
+  .reset_calib(reset_calib), // for IDES and CLKDIV reset
+  .set_calib(), 
+  .ready()
+);
+
+
+defparam Inst4_CLKDIVC.DIV_MODE="4";
+defparam Inst4_CLKDIVC.GSREN="false";
+CLKDIV Inst4_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_400m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_100m_a)
+);
+
+
+defparam Inst2_CLKDIVC.DIV_MODE="2";
+defparam Inst2_CLKDIVC.GSREN="false";
+CLKDIV Inst2_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_100m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_50m_a)
+);
+
+
+defparam Inst5_CLKDIVC.DIV_MODE="5";
+defparam Inst5_CLKDIVC.GSREN="false";
+CLKDIV Inst5_CLKDIVC(
+  .RESETN (~reset_calib),
+  .HCLKIN (clk_50m_a),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_10m_a)
+);
+
+DOut16 i_dout16(
+  .reset(~rst_n),
+  .clock(clk_10m_a),
+  .io_reset_calib(reset_calib),
+  .io_oser_pclk(clk_10m_a),
+  .io_oser_fclk(clk_50m_a),
+  .io_ides_pclk(clk_100m_a),
+  .io_ides_fclk(clk_400m_a),
+
+  .io_lvds_down_din(lvds_down_din),
+  .io_lvds_down_dout(lvds_down_dout),
+  .io_lvds_up_din(lvds_up_din),
+  .io_lvds_up_dout(lvds_up_dout),
+
+  .io_isOnline(isOnline),
+  .io_isLast(isLast),
+  .io_DCIn(DCIn),
+
+  .param_vendorID(`VENDORID),
+  .param_moduleID(`MODULEID),
+  .param_hwVersion(`HWVERSION),
+  .param_swVersion(`SWVERSION),
+  .param_batchID(`BATCHID),
+  .param_serial(`SERIAL),
+  .LED_PR(LED_PR),
+  .out(out),
+  .flt_0(flt_0),
+  .flt_1(flt_1)
+);
+
+endmodule
+
+
+
+