DC 同步功能； 基于IO的下级从机热插入

src/main/verilog/di16_top.v

@@ -2,7 +2,6 @@
 
 module di16_top(
 
-  input resetn,
   input clock, 
      
   input  lvds_up_din_p,
@@ -15,11 +14,17 @@ module di16_top(
   output lvds_down_dout_p,
   output lvds_down_dout_n,
 
+  output isOnline,
+  input  isLast,
+  input  DCIn,
+
   output        LED_PR,
   input  [15:0] in
 
 );
 
+wire resetn = 1'b1;
+
 wire clk_400m;
 wire clk_400m_a;
 wire clk_100m_a;
@@ -139,6 +144,10 @@ DIn16 i_din16(
   .io_lvds_up_din(lvds_up_din),
   .io_lvds_up_dout(lvds_up_dout),
 
+  .io_isOnline(isOnline),
+  .io_isLast(isLast),
+  .io_DCIn(DCIn),
+
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),