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DC 同步功能； 基于IO的下级从机热插入

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This commit is contained in:
RuigeLee
2024-05-11 14:57:42 +08:00
parent 451763301d
commit b264f729b4
5 changed files with 213 additions and 17 deletions
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5
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -17,6 +17,11 @@ class BackBoardSlvIO extends Bundle{
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val lvds_up_dout = Output(Bool())
val isOnline = Output(Bool())
val isLast = Input(Bool())
val DCIn = Input(Bool())
}

42
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -23,11 +23,13 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
val statusPR = RegEnable( Cat( downRegTemp(1).extract(0), downRegTemp(0).extract(7) ), 0.U, isCrcPass )
val statusER = RegInit(false.B)
val statusLE = RegInit(false.B)
val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
val statusNone = ~io.isLast
upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
upReg(1) := Cat( statusLE, statusER, statusPR.extract(1) )
upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
when( statusPage === 15.U ){
upReg(2) := 0.U
@@ -63,6 +65,9 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
val (usCounter, usTrigger) = Counter(Range(0, 10))
io.isOnline := false.B
val isUpdate = (statusSync & ~RegNext(io.DCIn) & io.DCIn) | (~statusSync)
}
@@ -217,16 +222,16 @@ with BackBoardSlvIn16{
inPin := in
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
digitalFilter(0) := downRegTemp(4)
digitalFilter(1) := downRegTemp(5)
}
val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }
when( statusPage === 0.U ){
upReg(2) := Cat( digitalIn(0).reverse )
upReg(3) := Cat( digitalIn(1).reverse )
upReg(2) := digitalInSync(0)
upReg(3) := digitalInSync(1)
upReg(4) := digitalFilter(0)
upReg(5) := digitalFilter(1)
}
@@ -237,8 +242,7 @@ with BackBoardSlvIn16{
trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
val outReg = RegInit(0.U(16.W))
val chsWire = Wire( Vec(16, UInt(2.W)) )
val outRegSync = Wire(UInt(16.W))
val mthodReg = RegInit(0.U(16.W))
val valueReg = RegInit(0.U(16.W))
@@ -246,7 +250,7 @@ trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
val outPin = Wire(UInt(16.W))
outPin :=
Mux(statusPR === 3.U, outReg, (mthodReg & valueReg) | (~mthodReg & outReg))
Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))
}
@@ -256,25 +260,31 @@ with BackBoardSlvStatusPR
with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W)))
val flt = IO(Input(Vec(2, Bool())))
val outReg = RegInit(0.U(16.W))
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(3), downRegTemp(2))
}
when( isCrcPass & downRegTemp(0)(3,0) === 1.U ){
when( isCrcPass & downRegTemp(0)(3,0) === 1.U & downRegTemp(2).extract(0) ){
mthodReg := Cat(downRegTemp(3), downRegTemp(2))
valueReg := Cat(downRegTemp(5), downRegTemp(4))
}
outRegSync := RegEnable( outReg, 0.U, isUpdate )
when( statusPage === 0.U ){
upReg(4) := Cat( ( 3 to 0 by -1).map{ i => chsWire(i) } )
upReg(5) := Cat( ( 7 to 4 by -1).map{ i => chsWire(i) } )
upReg(6) := Cat( ( 11 to 8 by -1).map{ i => chsWire(i) } )
upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
upReg(2) := outReg(7,0)
upReg(3) := outReg(15,8)
upReg(4) := Cat( ~flt(1), ~flt(0) )
}
for( i <- 0 until 8 ){
chsWire(i) := Mux( flt(0) === true.B, "b00".U, "b01".U)
chsWire(8+i) := Mux( flt(1) === true.B, "b00".U, "b01".U)
when( statusPage === 1.U ){
upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)
upReg(4) := mthodReg(7,0)
upReg(5) := mthodReg(15,8)
upReg(6) := valueReg(7,0)
upReg(7) := valueReg(15,8)
}
out := outPin