DC 同步功能；基于IO的下级从机热插入

2024-05-11 14:57:42 +08:00
parent 451763301d
commit b264f729b4
5 changed files with 213 additions and 17 deletions
--- a/1
+++ b/1
@@ -18,6 +18,7 @@ back:
 	# cp ./src/main/verilog/backBoardSlvTop.v ./generated/
 	cp ./src/main/verilog/oser_rst.v ./generated/
 	cp ./src/main/verilog/di16_top.v ./generated/
+	cp ./src/main/verilog/do16_top.v ./generated/
 	cp ./src/main/verilog/defineParam.v ./generated/