backboard

src/main/scala/backBoard/CDRBus.scala

@@ -0,0 +1,123 @@
+package MAC
+
+import chisel3._
+import chisel3.util._
+
+class CDRData extends Bundle{
+  val address  = UInt(6.W)
+  val register = UInt(8.W)
+  val data     = UInt(32.W)
+  val hash     = UInt(2.W)
+
+  def isHashPass = true.B
+
+}
+
+
+class CDRInBusIO() extends Bundle{
+  val dat = Input(Bool())
+
+
+  val latchDat = Decoupled(new CDRData)
+  val flush = Input(Bool())
+}
+
+
+
+class CDRInBus() extends Module{
+  val io: CDRInBusIO = IO(new CDRInBusIO())
+
+  val latchValid = RegInit(false.B)
+  val latchInfo = RegInit(0.U.asTypeof(new CDRData))
+  val shiftDat = RegInit(0.U((1+2+ ((new CDRData).getWidth) ).W))
+  val transInfo = shiftDat(1+2+((new CDRData).getWidth)-2,2).asTypeof(new CDRData)
+
+  val isHashPass = transInfo.isHashPass
+
+
+  when( flush ){
+    shiftDat   := 0.U
+    latchValid := false.B
+  } .elsewhen( shiftDat.extract(1+2+((new CDRData).getWidth)-1) =/= 1.U ){
+    shiftDat := Cat(shiftDat << 1 , io.dat)
+  } .elsewhen( shiftDat.extract(1+2+((new CDRData).getWidth)-1) === 1.U ){
+    when( passHash ){
+      latchValid := true.B
+      latchInfo  := transInfo
+    } .otherwise{
+      shiftDat   := 0.U
+    }
+  }
+
+  io.latachDat.valid := latchValid
+  io.latachDat.bits  := latchInfo
+
+}
+
+
+
+
+
+
+
+
+
+
+class CDR4InBusIO extends Bundle{
+  val dat    = Input( Vec(4, Bool()) )
+  val refClk = Input( Vec(4, Bool()) )
+
+  val syncDat = Decoupled(new CDRData)
+}
+
+class CDR4InBus extends Module{
+  val io: CDR4InBusIO = IO(new CDR4InBusIO)
+
+  val inBusAsync = ( 0 until 4 ).map{
+    Module(new CDRInBus)
+  }
+
+
+  val inBusToAsync = Wire( Vec(4, new AsyncBundle(new CDRInBus)) )
+  val inBusSyncIO = Vec(4, Decoupled(new CDRData) )
+
+  val inBusMuxValid = RegInit(false.B)
+  val inBusMuxInfo  = RegInit(0.U.asTypeof(new CDRData))
+
+  io.syncDat.valid := inBusMuxValid
+  io.syncDat.bits  := inBusMuxInfo
+
+  for( i <- 0 until 4 ){
+    inBusAsync(i).clock    := io.refClk(i).clock
+    inBusAsync(i).io.dat   := io.dat(i)
+    inBusAsync(i).io.flush := io.syncDat.fire
+
+    inBusToAsync(i) <> ToAsyncBundle( inBusSyncIO(i), AsyncQueueParams(sync=2) )
+      
+    withClockAndReset( io.refClk(i).clock, reset ) {
+      inBusAsync(i).io.syncDat <> FromAsyncBundle( inBusToAsync, 2 )      
+    }   
+  }
+
+  when( io.syncDat.fire ){
+    inBusMuxValid := false.B
+  } .elsewhen( ~inBusMuxValid ){
+    inBusMuxValid := inBusSyncIO.map{ x => x.valid }.reduce(_|_)
+    inBusMuxInfo  := Mux1H( inBusSyncIO.map{ x => (x.valid -> x.bits) })
+  }
+
+
+
+  ( 0 until 4).map{ i =>
+    ( 0 until i ).map{ j =>
+      assert( Mux(inBusSyncIO(i).valid & inBusSyncIO(j).valid, inBusSyncIO(i).bits.asUInt === inBusSyncIO(j).bits.asUInt, true.B ),
+      "Assert Failed, How can you pass the CRC check?!"  )
+    }
+  }
+
+
+}
+
+
+
+

src/main/scala/backBoard/LocalRegisters.scala

@@ -0,0 +1,36 @@
+package MAC
+
+import chisel3._
+import chisel3.util._
+
+// class LocalRegistersIO extends Bundle{
+//   val 
+// }
+
+
+
+class LocalRegisters(implicit p: Parameters) extends LazyModule{
+
+  val device = new SimpleDevice("slv",Seq("slv"))
+  val configNode = TLRegisterNode(
+    address = Seq(AddressSet(0x000L, 0x000000ffL)),
+    device = device,
+    concurrency = 1,
+    beatBytes = 32/8,
+    executable = true
+  )
+
+  lazy val module = new LocalRegImp(this){
+
+    val digitalDir = RegInit(0.U(32.W))
+
+
+    configNode.regmap(
+      ( 0 << 2 ) -> 
+        RegFieldGroup("DigitalDir", Some("Digital IO Direction"), Seq(
+          RegField(32, digitalDir , RegFieldDesc( "digitalDir", "digitalDir", reset = Some(0))) ,
+        )),
+    )
+
+  }
+}

src/main/scala/backBoard/StatusControl.scala

@@ -0,0 +1,53 @@
+package MAC
+
+import chisel3._
+import chisel3.util._
+
+
+class StatusControlIO extends Bundle{
+
+}
+
+
+class StatusControl(implicit p: Parameters) extends LazyModule{
+
+  val upStreamReq    = 
+  val downStreamResp = 
+
+  val upStreamResq   = 
+  val downStreamReq  = 
+
+
+  val register = LazyModule(new LocalRegisters)
+
+
+  lazy val module = new StatusControlImp(this){
+    val io: StatusControlIO = IO(new StatusControlIO)
+
+    def IDLE            = 0.U
+    def UPSTREAM_REQ    = 1.U
+    def DOWNSTREAM_REQ  = 2.U
+    def UPSTREAM_RESP   = 3.U
+    def DOWNSTREAM_RESP = 4.U
+
+    val stateNext = Wire( UInt(3.W) )
+    val stateCurr = RegNext(stateNext, 0.U)
+
+    stateNext := Mux1H(Seq(
+      (stateCurr === IDLE)            -> ,
+      (stateCurr === UPSTREAM_REQ)    -> ,
+      (stateCurr === DOWNSTREAM_REQ)  -> ,
+      (stateCurr === UPSTREAM_RESP)   -> ,
+      (stateCurr === DOWNSTREAM_RESP) -> ,
+    ))
+
+
+
+
+
+
+
+
+
+  }
+}