remvoe pad and minFL

src/main/scala/Switch/MacRegisters.scala

@@ -26,7 +26,6 @@ class Mac_Config_Bundle extends Bundle{
   val TxClk               = Input(Bool())
   val RxClk               = Input(Bool())
 
-  val r_Pad       = Output(Bool())
   val r_HugEn     = Output(Bool())
   val r_CrcEn     = Output(Bool())
   val r_DlyCrcEn  = Output(Bool())
@@ -42,7 +41,6 @@ class Mac_Config_Bundle extends Bundle{
   val r_IPGT      = Output(UInt(7.W))
   val r_IPGR1     = Output(UInt(7.W))
   val r_IPGR2     = Output(UInt(7.W))
-  val r_MinFL     = Output(UInt(16.W))
   val r_CollValid = Output(UInt(6.W))
   val r_MiiNoPre  = Output(Bool())
   val r_ClkDiv    = Output(UInt(8.W))
@@ -94,7 +92,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     val (int, _) = outer.int_node.out(0)
 
 
-    val Pad       = RegInit(true.B)
     val HugEn     = RegInit(false.B)
     val CrcEn     = RegInit(true.B)
     val DlyCrcEn  = RegInit(false.B)
@@ -122,8 +119,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     val IPGR1    = RegInit("h0C".U(7.W))    // IPGR1 Register
     val IPGR2    = RegInit("h12".U(7.W))
 
-    val minFL = RegInit("h0040".U(16.W))
-
     val collValid = RegInit("h3f".U(6.W))
 
     val clkDiv = RegInit("h64".U(8.W))
@@ -183,7 +178,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
           RegField(1, DlyCrcEn, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ),
           RegField(1, CrcEn   , RegFieldDesc( "CrcEn", "CrcEn",       reset=Some(1)) ),
           RegField.r(1, 1.U   , RegFieldDesc( "HugEn", "HugEn",       reset=Some(0)) ),
-          RegField(1, Pad     , RegFieldDesc( "Pad", "Pad",           reset=Some(1)) ),
+          RegField.r(1, 1.U   , RegFieldDesc( "Pad", "Pad",           reset=Some(1)) ),
           RegField.r(1, 1.U,    RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) )
         )),
 
@@ -220,9 +215,9 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
       ( 6 << 2 ) ->
         RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq(
-          RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600)))) ++
+          RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))) ++
-          RegField.bytes(minFL, Some(RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))))
+          RegField.r(16, 64.U, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040)))
-        ),
+        )),
       ( 7 << 2 ) ->
         RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq(
           RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))),
@@ -330,7 +325,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
 
 
-    io.r_Pad       := Pad
     io.r_HugEn     := HugEn
     io.r_CrcEn     := CrcEn
     io.r_DlyCrcEn  := DlyCrcEn
@@ -345,7 +339,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     io.r_IPGT      := IPGT
     io.r_IPGR1     := IPGR1
     io.r_IPGR2     := IPGR2
-    io.r_MinFL     := minFL
     io.r_CollValid := collValid
     io.r_MiiNoPre  := miiNoPre
     io.r_ClkDiv    := clkDiv

src/main/scala/Switch/SwitchMux.scala

@@ -59,8 +59,6 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
 
 
     def PerPacketCrcEn = true.B
-    def PerPacketPad   = true.B
-
 
 
 
@@ -80,7 +78,6 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
   txBuff.io.enq.req.valid := txReqValid && stateCur === stateIdle
   txBuff.io.enq.req.bits.txLength := io.r_TxLen
   txBuff.io.enq.req.bits.PerPacketCrcEn := PerPacketCrcEn
-  txBuff.io.enq.req.bits.PerPacketPad := PerPacketPad
 
 
 

src/main/scala/Switch/TxBuff.scala

@@ -10,7 +10,6 @@ import chisel3.util._
 class Transmit_Req_Bundle extends Bundle{
   val txLength       = UInt(16.W)
   val PerPacketCrcEn = Bool()
-  val PerPacketPad   = Bool()
 }
 
 class Transmit_Resp_Bundle extends Bundle{

src/main/scala/Switch/mac/MAC.scala

@@ -141,7 +141,6 @@ val MRxErr_Lb                  = Wire(Bool())
 val MRxD_Lb                    = Wire(UInt(4.W))
 val Transmitting               = Wire(Bool())
 val r_DlyCrcEn                 = Wire(Bool())
-val r_MinFL                    = Wire(UInt(16.W))
 val DribbleNibble              = Wire(Bool())
 val LoadRxStatus               = Wire(Bool())
 val r_HASH0                    = Wire(UInt(32.W))
@@ -157,12 +156,10 @@ val TxE_IRQ                    = Wire(Bool())
 val RxB_IRQ                    = Wire(Bool())
 val RxE_IRQ                    = Wire(Bool())
 val Busy_IRQ                   = Wire(Bool())
-val r_Pad                      = Wire(Bool())
 val r_CrcEn                    = Wire(Bool())
 val r_FullD                    = Wire(Bool())
 val r_NoPre                    = Wire(Bool())
 val StartTxDone                = Wire(Bool())
-val PerPacketPad               = Wire(Bool())
 val PerPacketCrcEn             = Wire(Bool())
 val LateCollision              = Wire(Bool())
 val DeferIndication            = Wire(Bool())
@@ -179,7 +176,6 @@ dontTouch(MRxErr_Lb                  )
 dontTouch(MRxD_Lb                    )
 dontTouch(Transmitting               )
 dontTouch(r_DlyCrcEn                 )
-dontTouch(r_MinFL                    )
 dontTouch(DribbleNibble              )
 dontTouch(LoadRxStatus               )
 dontTouch(r_HASH0                    )
@@ -195,12 +191,10 @@ dontTouch(TxE_IRQ                    )
 dontTouch(RxB_IRQ                    )
 dontTouch(RxE_IRQ                    )
 dontTouch(Busy_IRQ                   )
-dontTouch(r_Pad                      )
 dontTouch(r_CrcEn                    )
 dontTouch(r_FullD                    )
 dontTouch(r_NoPre                    )
 dontTouch(StartTxDone                )
-dontTouch(PerPacketPad               )
 dontTouch(PerPacketCrcEn             )
 dontTouch(LateCollision              )
 dontTouch(DeferIndication            )
@@ -230,7 +224,6 @@ io.cfg.StartTxDone         := StartTxDone
 io.cfg.TxClk               := io.mii.mtx_clk_pad_i
 io.cfg.RxClk               := io.mii.mrx_clk_pad_i
 
-r_Pad       := io.cfg.r_Pad
 r_CrcEn     := io.cfg.r_CrcEn
 r_DlyCrcEn  := io.cfg.r_DlyCrcEn
 r_FullD     := io.cfg.r_FullD
@@ -245,7 +238,6 @@ r_HASH1     := io.cfg.r_HASH1
 r_IPGT      := io.cfg.r_IPGT
 r_IPGR1     := io.cfg.r_IPGR1
 r_IPGR2     := io.cfg.r_IPGR2
-r_MinFL     := io.cfg.r_MinFL
 r_CollValid := io.cfg.r_CollValid
 r_MiiNoPre  := io.cfg.r_MiiNoPre
 r_ClkDiv    := io.cfg.r_ClkDiv
@@ -341,11 +333,9 @@ txethmac.io.TxEndFrm        := TxEndFrm
 txethmac.io.TxData          := TxData
 txethmac.io.CarrierSense    := TxCarrierSense
 txethmac.io.Collision       := Collision
-txethmac.io.Pad             := r_Pad | PerPacketPad
 txethmac.io.CrcEn           := r_CrcEn | PerPacketCrcEn
 txethmac.io.FullD           := r_FullD
 txethmac.io.DlyCrcEn        := r_DlyCrcEn
-txethmac.io.MinFL           := r_MinFL
 txethmac.io.IPGT            := r_IPGT
 txethmac.io.IPGR1           := r_IPGR1
 txethmac.io.IPGR2           := r_IPGR2
@@ -460,7 +450,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   wishbone.io.CarrierSenseLost := CarrierSenseLost
 
   PerPacketCrcEn := wishbone.io.PerPacketCrcEn
-  PerPacketPad   := wishbone.io.PerPacketPad
 
   wishbone.io.r_TxEn     := r_TxEn
   wishbone.io.r_RxEn     := r_RxEn

src/main/scala/Switch/mac/MacTilelink.scala

@@ -41,7 +41,6 @@ abstract class MacTileLinkBase() extends Module{
     val DeferLatched     = Input(Bool())     // Defer indication (Frame was defered before sucessfully sent)
     val CarrierSenseLost = Input(Bool())     // Carrier Sense was lost during the frame transmission
     val PerPacketCrcEn = Output(Bool())     // Per packet crc enable
-    val PerPacketPad   = Output(Bool())     // Per packet pading
 
     //Register
     val r_TxEn    = Input(Bool())          // Transmit enable
@@ -136,7 +135,6 @@ abstract class MacTileLinkBase() extends Module{
   val txAbortPulse                = io.TxAbortSync             & ~RegNext(io.TxAbortSync, false.B)
 
   
-  io.PerPacketPad    := RegEnable(io.txDeq.req.bits.PerPacketPad,   false.B, io.txDeq.req.fire)
   io.PerPacketCrcEn  := RegEnable(io.txDeq.req.bits.PerPacketCrcEn, false.B, io.txDeq.req.fire)
 
   when( io.txDeq.req.fire ){

src/main/scala/Switch/mac/MacTx.scala

@@ -11,11 +11,10 @@ class MacTxIO extends Bundle{
   val TxData          = Input(UInt(8.W))         // Transmit packet data byte
   val CarrierSense    = Input(Bool())         // Carrier sense (synchronized)
   val Collision       = Input(Bool())         // Collision (synchronized)
-  val Pad             = Input(Bool())         // Pad enable (from register)
+
   val CrcEn           = Input(Bool())         // Crc enable (from register)
   val FullD           = Input(Bool())         // Full duplex (from register)
   val DlyCrcEn        = Input(Bool())         // Delayed Crc enabled (from register)
-  val MinFL           = Input(UInt(16.W))         // Minimum frame length (from register)
   val IPGT            = Input(UInt(7.W))         // Back to back transmit inter packet gap parameter (from register)
   val IPGR1           = Input(UInt(7.W))         // Non back to back transmit inter packet gap parameter IPGR1 (from register)
   val IPGR2           = Input(UInt(7.W))         // Non back to back transmit inter packet gap parameter IPGR2 (from register)
@@ -98,10 +97,10 @@ trait MacTxFSM { this: MacTxBase =>
   StartData(0) := ~io.Collision & (StatePreamble & NibCntEq15 | StateData(1) & ~io.TxEndFrm)
   StartData(1) := ~io.Collision & StateData(0)
 
-  val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & io.Pad & ~NibbleMinFl
+  val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & ~NibbleMinFl
 
   StartFCS :=
-    (~io.Collision & StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & io.CrcEn) |
+    (~io.Collision & StateData(1) & io.TxEndFrm & NibbleMinFl & io.CrcEn) |
     (~io.Collision & StatePAD & NibbleMinFl & io.CrcEn)
 
   StartJam := (io.Collision ) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS)
@@ -192,7 +191,7 @@ trait MacTxCounter { this: MacTxBase =>
     NibCnt := NibCnt + 1.U
   }
 
-  NibbleMinFl := NibCnt >= (((io.MinFL-4.U)<<1) - 1.U)  // FCS should not be included in NibbleMinFl
+  NibbleMinFl := NibCnt >= (((64.U-4.U)<<1) - 1.U)  // FCS should not be included in NibbleMinFl
 
   ExcessiveDefer := NibCnt(13,0) === "h17b7".U & ~io.ExDfrEn;   // 6071 nibbles
 
@@ -297,7 +296,7 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
 
   io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS)
   val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
-  io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
+  io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & NibbleMinFl & ~io.CrcEn)
   io.LateCollision := StartJam & ~ColWindow
   io.MaxCollisionOccured := StartJam & ColWindow;
   StateSFD := StatePreamble & NibCntEq15;