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16相位操作还是卡

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This commit is contained in:
Ruige Lee
2025-08-11 18:13:58 +08:00
parent 24cbc2723c
commit b0b221e8b0
1 changed files with 11 additions and 70 deletions
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81
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -72,82 +72,23 @@ trait CDRInMultiSample{ this: CDRInBase =>
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(16, Bool()))) val multiCLK = IO(Input(Vec(16, Bool())))
// val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
val sampleReg = for( i <- 0 until 16 ) yield { val sampleReg = Wire(Vec(23, Bool()))
withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
for( i <- 0 until 16 ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
}
for( i <- 16 until 23 ){
sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
} }
val flitReg =
if(false){ val asyncSerDat = PopCount(sampleReg) >= 12.U
for( i <- 0 until 16 ) yield {
sampleReg(i)
}
} else if (true){ //5选3 多数投票 滤波
for( i <- 0 until 16 ) yield {
(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i+0)%16) & sampleReg((i+1)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i+0)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+0)%16) & sampleReg((i+1)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+0)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-0)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16))
}
} else { //3选2 多数投票 滤波
for( i <- 0 until 16 ) yield {
(sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
(sampleReg((i+0)%16) & sampleReg((i+1)%16))
}
}
val arbLock = Reg(UInt( 16.W )) // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
when( flitReg(0) ^ flitReg(1) ){
arbLock := "b1".U(16.W) << 2
} .elsewhen( flitReg(1) ^ flitReg(2) ){
arbLock := "b1".U(16.W) << 3
} .elsewhen( flitReg(2) ^ flitReg(3) ){
arbLock := "b1".U(16.W) << 4
} .elsewhen( flitReg(3) ^ flitReg(4) ){
arbLock := "b1".U(16.W) << 5
} .elsewhen( flitReg(4) ^ flitReg(5) ){
arbLock := "b1".U(16.W) << 6
} .elsewhen( flitReg(5) ^ flitReg(6) ){
arbLock := "b1".U(16.W) << 7
} .elsewhen( flitReg(6) ^ flitReg(7) ){
arbLock := "b1".U(16.W) << 8
} .elsewhen( flitReg(7) ^ flitReg(8) ){
arbLock := "b1".U(16.W) << 9
} .elsewhen( flitReg(8) ^ flitReg(9) ){
arbLock := "b1".U(16.W) << 10
} .elsewhen( flitReg(9) ^ flitReg(10) ){
arbLock := "b1".U(16.W) << 11
} .elsewhen( flitReg(10) ^ flitReg(11) ){
arbLock := "b1".U(16.W) << 12
} .elsewhen( flitReg(11) ^ flitReg(12) ){
arbLock := "b1".U(16.W) << 13
} .elsewhen( flitReg(12) ^ flitReg(13) ){
arbLock := "b1".U(16.W) << 14
} .elsewhen( flitReg(13) ^ flitReg(14) ){
arbLock := "b1".U(16.W) << 15
} .elsewhen( flitReg(14) ^ flitReg(15) ){
arbLock := "b1".U(16.W) << 0
} .elsewhen( flitReg(15) ^ flitReg(0) ){
arbLock := "b1".U(16.W) << 1
}
val asyncSerDat =
Mux1H(
(for { i <- 0 until clkNum } yield {
(arbLock === (1.U << i)) -> flitReg(i)
})
)
syncSerDat := ShiftRegister( asyncSerDat, 2 ) syncSerDat := ShiftRegister( asyncSerDat, 2 )