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临时调试修改，需要revert

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This commit is contained in:
RuigeLee
2023-12-07 11:10:43 +08:00
parent 1f898a7173
commit afd21f6913
3 changed files with 156 additions and 100 deletions
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187
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -8,18 +8,19 @@ import chisel3.util._
class FSMC_Port_Bundle extends Bundle{ class FSMC_Port_Bundle extends Bundle{
val addr = Input(UInt(10.W)) // val addr = Input(UInt(10.W))
val dataIn = Input(UInt(16.W)) val ADIn = Input(UInt(16.W))
val dataOut = Output(UInt(16.W)) val ADOut = Output(UInt(16.W))
val dataOEn = Output(Bool()) val ADOEn = Output(Bool())
val cen = Input(Bool()) val csn = Input(Bool())
val oen = Input(Bool()) val rdn = Input(Bool())
val wen = Input(Bool()) val wrn = Input(Bool())
val advn = Input(Bool())
} }
class BackBoardMstIO extends Bundle{ class BackBoardMstIO extends Bundle{
val FSMC = new FSMC_Port_Bundle // val FSMC = new FSMC_Port_Bundle
// val reset = Input(Bool()) // val reset = Input(Bool())
val reset_calib = Input(Bool()) val reset_calib = Input(Bool())
@@ -34,6 +35,9 @@ val reset_calib = Input(Bool())
val cdrErr = Output(Bool()) val cdrErr = Output(Bool())
val crcErr = Output(Bool()) val crcErr = Output(Bool())
val linkErr = Output(Bool()) val linkErr = Output(Bool())
val testFail = Output(Bool())
val testDone = Output(Bool())
} }
// class Master_Status_Bundle extends Bundle{ // class Master_Status_Bundle extends Bundle{
@@ -105,94 +109,127 @@ class BackBoardMstBase extends Module{ //10M
trait BackBoardMstFSMC{ this: BackBoardMstBase => // trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B ) // // val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B ) // // val fsmcADInSync = ShiftRegister( io.FSMC.ADIn, 2, 0.U, true.B )
val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B ) // val fsmcCSnSync = ShiftRegister( io.FSMC.csn, 2, true.B, true.B )
val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B ) // val fsmcRDnSync = ShiftRegister( io.FSMC.rdn, 2, true.B, true.B )
val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B ) // val fsmcWRnSync = ShiftRegister( io.FSMC.wrn, 2, true.B, true.B )
// val fsmcADVnSync = ShiftRegister( io.FSMC.advn, 2, true.B, true.B )
io.FSMC.dataOEn := io.FSMC.oen
val isAccessSRAM = ~fsmcAddrSync.extract(9)
val isAccessReg = fsmcAddrSync.extract(9)
val activeAddr = fsmcAddrSync(8,0)
val regOut = Wire(UInt(16.W))
mirrorDown.io.enw := (~fsmcCEnSync & isAccessSRAM & (~fsmcWEnSync) )
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := fsmcdataInSync
mirrorUp.io.enr := (~fsmcCEnSync & isAccessSRAM & (~fsmcOEnSync) )
mirrorUp.io.addrr := activeAddr
// io.FSMC.ADOEn := fsmcRDnSync
// val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVnSync )
// val isAccessSRAM = ~latchAddr.extract(9)
// val isAccessReg = latchAddr.extract(9)
// val activeAddr = latchAddr(8,0)
// val regOut = Wire(UInt(16.W))
// mirrorDown.io.enw := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B )
// mirrorDown.io.addrw := activeAddr
// mirrorDown.io.dataw := io.FSMC.ADIn
// mirrorUp.io.enr := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.rdn, 2, false.B, true.B )
// mirrorUp.io.addrr := activeAddr
io.FSMC.dataOut := Mux( isAccessReg, regOut, mirrorUp.io.datar) // io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
regOut := Mux1H(Seq( // regOut := Mux1H(Seq(
( activeAddr === 0.U) -> // ( activeAddr === 0.U) ->
Cat( // Cat(
statusCDRErr , // statusCDRErr ,
statusCRCErr , // statusCRCErr ,
statusLinkErr, // statusLinkErr,
statusSynch , // statusSynch ,
statusInit // statusInit
), // ),
( activeAddr === 1.U) -> // ( activeAddr === 1.U) ->
Cat( // Cat(
ctrlTransmit, // ctrlTransmit,
0.U(1.W), // 0.U(1.W),
0.U(1.W), // 0.U(1.W),
0.U(1.W), // 0.U(1.W),
ctrlSynch, // ctrlSynch,
ctrlInit // ctrlInit
), // ),
( activeAddr === 2.U) -> slvNum, // ( activeAddr === 2.U) -> slvNum,
( activeAddr === 3.U) -> slvOffLine, // ( activeAddr === 3.U) -> slvOffLine,
)) // ))
// when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){ // // when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 0.U) ){
// status := fsmcdataInSync // // status := io.FSMC.ADIn
// } // // }
when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){ // when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 1.U) ){
ctrlTransmit := fsmcdataInSync.extract(5) // ctrlTransmit := io.FSMC.ADIn.extract(5)
when( fsmcdataInSync.extract(4) ){ // when( io.FSMC.ADIn.extract(4) ){
statusCDRErr := false.B // statusCDRErr := false.B
} // }
when( fsmcdataInSync.extract(3) ){ // when( io.FSMC.ADIn.extract(3) ){
statusCRCErr := false.B // statusCRCErr := false.B
} // }
when( fsmcdataInSync.extract(2) ){ // when( io.FSMC.ADIn.extract(2) ){
statusLinkErr := false.B // statusLinkErr := false.B
} // }
ctrlSynch := fsmcdataInSync.extract(1) // ctrlSynch := io.FSMC.ADIn.extract(1)
ctrlInit := fsmcdataInSync.extract(0) // ctrlInit := io.FSMC.ADIn.extract(0)
// }
// // when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 2.U) ){
// // slvNum := io.FSMC.ADIn
// // }
// when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 3.U) ){
// slvOffLine := io.FSMC.ADIn
// }
// }
trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
when( powerUpCnt === 500.U ){
ctrlInit := true.B
} }
// when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 2.U) ){ ctrlTransmit := statusInit
// slvNum := fsmcdataInSync
// }
when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 3.U) ){
slvOffLine := fsmcdataInSync
}
mirrorDown.io.enw := true.B
mirrorDown.io.addrw := powerUpCnt
mirrorDown.io.dataw := "h5555".U
mirrorUp.io.enr := false.B
mirrorUp.io.addrr := 0.U
val testDone = RegInit(false.B)
val testFail = RegInit(false.B)
io.testDone := ~testDone
io.testFail := ~testFail
} }
abstract class BackBoardMstLVDSBase extends BackBoardMstBase with BackBoardMstFSMC{
abstract class BackBoardMstLVDSBase extends BackBoardMstBase
// with BackBoardMstFSMC
with BackBoardMstSim
{
val frame_info_update_en = RegInit(false.B) val frame_info_update_en = RegInit(false.B)
@@ -280,7 +317,11 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.slave_link_num_valid ){ when( lvdsMst.io.slave_link_num_valid ){
when( slvNum === lvdsMst.io.slave_link_num - 1.U ){ when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
stateCur := 7.U stateCur := 7.U
testDone := true.B
testFail := false.B
} .otherwise{ } .otherwise{
testDone := false.B
testFail := true.B
printf("Initialization failed, waitting for timeout!\n") printf("Initialization failed, waitting for timeout!\n")
} }
} }

44
src/main/verilog/backBoardMstTop.v
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@@ -11,14 +11,21 @@ module master_top(
output lvds_down_dout_p, output lvds_down_dout_p,
output lvds_down_dout_n, output lvds_down_dout_n,
output cdrErr ,
output crcErr ,
output linkErr,
output testDone,
output testFail
input [9:0] io_FSMC_addr, // input [9:0] io_FSMC_addr,
input [15:0] io_FSMC_dataIn, // input [15:0] io_FSMC_dataIn,
output [15:0] io_FSMC_dataOut, // output [15:0] io_FSMC_dataOut,
output io_FSMC_dataOEn, // output io_FSMC_dataOEn,
input io_FSMC_cen, // input io_FSMC_cen,
input io_FSMC_oen, // input io_FSMC_oen,
input io_FSMC_wen // input io_FSMC_wen
); );
@@ -122,13 +129,13 @@ CLKDIV Inst5_CLKDIVC(
BackBoardMst i_BackBoardMst( BackBoardMst i_BackBoardMst(
.io_FSMC_addr(io_FSMC_addr), // .io_FSMC_addr(io_FSMC_addr),
.io_FSMC_dataIn(io_FSMC_dataIn), // .io_FSMC_dataIn(io_FSMC_dataIn),
.io_FSMC_dataOut(io_FSMC_dataOut), // .io_FSMC_dataOut(io_FSMC_dataOut),
.io_FSMC_dataOEn(io_FSMC_dataOEn), // .io_FSMC_dataOEn(io_FSMC_dataOEn),
.io_FSMC_cen(io_FSMC_cen), // .io_FSMC_cen(io_FSMC_cen),
.io_FSMC_oen(io_FSMC_oen), // .io_FSMC_oen(io_FSMC_oen),
.io_FSMC_wen(io_FSMC_wen), // .io_FSMC_wen(io_FSMC_wen),
.reset(~rst_n), .reset(~rst_n),
.clock(clk_10m_a), .clock(clk_10m_a),
@@ -139,7 +146,14 @@ BackBoardMst i_BackBoardMst(
.io_ides_fclk(clk_400m_a), .io_ides_fclk(clk_400m_a),
.io_lvds_down_dout(lvds_down_dout), .io_lvds_down_dout(lvds_down_dout),
.io_lvds_up_din(lvds_up_din) .io_lvds_up_din(lvds_up_din),
.io_cdrErr (cdrErr),
.io_crcErr (crcErr),
.io_linkErr(linkErr),
.io_testDone(testDone),
.io_testFail(testFail)
); );

25
src/main/verilog/backBoardSlvTop.v
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@@ -15,7 +15,8 @@ module slave_top(
output lvds_down_dout_p, output lvds_down_dout_p,
output lvds_down_dout_n, output lvds_down_dout_n,
inout [31:0] digitalIO // inout [31:0] digitalIO
output [7:0] digitalIO
); );
@@ -130,18 +131,18 @@ CLKDIV Inst5_CLKDIVC(
generate // generate
for( genvar i = 0; i < 32; i = i + 1 ) begin // for( genvar i = 0; i < 32; i = i + 1 ) begin
IOBUF uut( // IOBUF uut(
.O(in[i]), // .O(in[i]),
.IO(digitalIO[i]), // .IO(digitalIO[i]),
.I(out[i]), // .I(out[i]),
.OEN(~oe[i]) // .OEN(~oe[i])
); // );
end // end
endgenerate // endgenerate
assign digitalIO = out[7:0];
BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO( BackBoardSlvDigitalIO i_BackBoardSlvDigitalIO(
.reset(~rst_n), .reset(~rst_n),