临时调试修改，需要revert
This commit is contained in:
RuigeLee
@@ -8,18 +8,19 @@ import chisel3.util._
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class FSMC_Port_Bundle extends Bundle{
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val addr = Input(UInt(10.W))
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val dataIn = Input(UInt(16.W))
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val dataOut = Output(UInt(16.W))
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val dataOEn = Output(Bool())
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val cen = Input(Bool())
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val oen = Input(Bool())
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val wen = Input(Bool())
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// val addr = Input(UInt(10.W))
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val ADIn = Input(UInt(16.W))
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val ADOut = Output(UInt(16.W))
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val ADOEn = Output(Bool())
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val csn = Input(Bool())
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val rdn = Input(Bool())
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val wrn = Input(Bool())
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val advn = Input(Bool())
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}
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class BackBoardMstIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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// val FSMC = new FSMC_Port_Bundle
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// val reset = Input(Bool())
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val reset_calib = Input(Bool())
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@@ -34,6 +35,9 @@ val reset_calib = Input(Bool())
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val cdrErr = Output(Bool())
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val crcErr = Output(Bool())
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val linkErr = Output(Bool())
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val testFail = Output(Bool())
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val testDone = Output(Bool())
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}
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// class Master_Status_Bundle extends Bundle{
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@@ -105,94 +109,127 @@ class BackBoardMstBase extends Module{ //10M
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trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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// trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
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val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
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val fsmcCEnSync = ShiftRegister( io.FSMC.cen, 2, true.B, true.B )
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val fsmcOEnSync = ShiftRegister( io.FSMC.oen, 2, true.B, true.B )
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val fsmcWEnSync = ShiftRegister( io.FSMC.wen, 2, true.B, true.B )
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io.FSMC.dataOEn := io.FSMC.oen
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val isAccessSRAM = ~fsmcAddrSync.extract(9)
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val isAccessReg = fsmcAddrSync.extract(9)
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val activeAddr = fsmcAddrSync(8,0)
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val regOut = Wire(UInt(16.W))
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mirrorDown.io.enw := (~fsmcCEnSync & isAccessSRAM & (~fsmcWEnSync) )
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mirrorDown.io.addrw := activeAddr
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mirrorDown.io.dataw := fsmcdataInSync
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// // val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
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// // val fsmcADInSync = ShiftRegister( io.FSMC.ADIn, 2, 0.U, true.B )
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// val fsmcCSnSync = ShiftRegister( io.FSMC.csn, 2, true.B, true.B )
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// val fsmcRDnSync = ShiftRegister( io.FSMC.rdn, 2, true.B, true.B )
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// val fsmcWRnSync = ShiftRegister( io.FSMC.wrn, 2, true.B, true.B )
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// val fsmcADVnSync = ShiftRegister( io.FSMC.advn, 2, true.B, true.B )
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mirrorUp.io.enr := (~fsmcCEnSync & isAccessSRAM & (~fsmcOEnSync) )
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mirrorUp.io.addrr := activeAddr
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// io.FSMC.ADOEn := fsmcRDnSync
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// val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVnSync )
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// val isAccessSRAM = ~latchAddr.extract(9)
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// val isAccessReg = latchAddr.extract(9)
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// val activeAddr = latchAddr(8,0)
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// val regOut = Wire(UInt(16.W))
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// mirrorDown.io.enw := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B )
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// mirrorDown.io.addrw := activeAddr
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// mirrorDown.io.dataw := io.FSMC.ADIn
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// mirrorUp.io.enr := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.rdn, 2, false.B, true.B )
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// mirrorUp.io.addrr := activeAddr
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io.FSMC.dataOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
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// io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
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regOut := Mux1H(Seq(
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( activeAddr === 0.U) ->
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Cat(
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statusCDRErr ,
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statusCRCErr ,
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statusLinkErr,
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statusSynch ,
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statusInit
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),
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( activeAddr === 1.U) ->
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Cat(
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ctrlTransmit,
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0.U(1.W),
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0.U(1.W),
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0.U(1.W),
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ctrlSynch,
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ctrlInit
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),
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( activeAddr === 2.U) -> slvNum,
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( activeAddr === 3.U) -> slvOffLine,
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))
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// regOut := Mux1H(Seq(
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// ( activeAddr === 0.U) ->
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// Cat(
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// statusCDRErr ,
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// statusCRCErr ,
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// statusLinkErr,
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// statusSynch ,
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// statusInit
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// ),
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// ( activeAddr === 1.U) ->
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// Cat(
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// ctrlTransmit,
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// 0.U(1.W),
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// 0.U(1.W),
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// 0.U(1.W),
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// ctrlSynch,
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// ctrlInit
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// ),
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// ( activeAddr === 2.U) -> slvNum,
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// ( activeAddr === 3.U) -> slvOffLine,
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// ))
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// when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 0.U) ){
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// status := fsmcdataInSync
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// }
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// // when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 0.U) ){
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// // status := io.FSMC.ADIn
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// // }
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when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 1.U) ){
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// when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 1.U) ){
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ctrlTransmit := fsmcdataInSync.extract(5)
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// ctrlTransmit := io.FSMC.ADIn.extract(5)
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when( fsmcdataInSync.extract(4) ){
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statusCDRErr := false.B
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}
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when( fsmcdataInSync.extract(3) ){
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statusCRCErr := false.B
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}
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when( fsmcdataInSync.extract(2) ){
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statusLinkErr := false.B
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}
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// when( io.FSMC.ADIn.extract(4) ){
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// statusCDRErr := false.B
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// }
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// when( io.FSMC.ADIn.extract(3) ){
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// statusCRCErr := false.B
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// }
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// when( io.FSMC.ADIn.extract(2) ){
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// statusLinkErr := false.B
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// }
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ctrlSynch := fsmcdataInSync.extract(1)
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ctrlInit := fsmcdataInSync.extract(0)
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// ctrlSynch := io.FSMC.ADIn.extract(1)
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// ctrlInit := io.FSMC.ADIn.extract(0)
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// }
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// // when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 2.U) ){
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// // slvNum := io.FSMC.ADIn
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// // }
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// when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 3.U) ){
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// slvOffLine := io.FSMC.ADIn
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// }
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// }
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trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
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val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
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when( powerUpCnt === 500.U ){
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ctrlInit := true.B
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}
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// when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 2.U) ){
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// slvNum := fsmcdataInSync
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// }
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ctrlTransmit := statusInit
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when( (~fsmcCEnSync & isAccessReg & (~fsmcWEnSync) ) & ( activeAddr === 3.U) ){
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slvOffLine := fsmcdataInSync
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}
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mirrorDown.io.enw := true.B
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mirrorDown.io.addrw := powerUpCnt
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mirrorDown.io.dataw := "h5555".U
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mirrorUp.io.enr := false.B
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mirrorUp.io.addrr := 0.U
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val testDone = RegInit(false.B)
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val testFail = RegInit(false.B)
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io.testDone := ~testDone
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io.testFail := ~testFail
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}
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abstract class BackBoardMstLVDSBase extends BackBoardMstBase with BackBoardMstFSMC{
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abstract class BackBoardMstLVDSBase extends BackBoardMstBase
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// with BackBoardMstFSMC
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with BackBoardMstSim
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{
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val frame_info_update_en = RegInit(false.B)
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@@ -280,7 +317,11 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
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when( lvdsMst.io.slave_link_num_valid ){
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when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
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stateCur := 7.U
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testDone := true.B
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testFail := false.B
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} .otherwise{
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testDone := false.B
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testFail := true.B
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printf("Initialization failed, waitting for timeout!\n")
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}
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}
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