执行第一个task块

2025-05-12 15:41:11 +08:00
parent e079103037
commit afa1b9864f
5 changed files with 542 additions and 13 deletions
--- a/tb/shinTest/ShinTopBareTb.v
+++ b/tb/shinTest/ShinTopBareTb.v
@@ -0,0 +1,713 @@
+`timescale 1 ns / 1 ps
+
+
+module ShinTopTb(
+
+);
+
+    reg clock;
+    reg reset;
+    reg clk8x;
+
+    wire [3:0] dDat_w;
+    wire [3:0] uDat_w;
+
+
+
+  reg [63:0] timeStamp = 0;
+
+  reg [10:0] sram_w_0_addrw;
+  reg [7:0]  sram_w_0_dataw;
+  reg        sram_w_0_enw = 1'b0;
+  reg txCmf = 1'b0;
+
+  reg        req_valid = 1'b0;
+  reg [14:0] req_bits_txAddr;
+  reg [14:0] req_bits_rxAddr;
+  reg [11:0] req_bits_length;
+
+ShinTop s_ShinTop_Mst(
+  .clock(clock),
+  .reset(reset),
+
+  .io_clk8x(clk8x),
+  .io_dDatIn(1'b0),
+  .io_dDatOut(dDat_w[0]),
+  .io_uDatIn(uDat_w[0]),
+  .io_uDatOut(),
+  
+  .io_timeStamp(timeStamp),
+
+  
+  .io_dSMdeq_0(1'b0),
+  .io_dSMdeq_1(1'b0),
+  .io_dSMdeq_2(1'b0),
+  .io_dSMdeq_3(1'b0),
+  .io_uSMenq_0(txCmf),
+  .io_uSMenq_1(1'b0),
+  .io_uSMenq_2(1'b0),
+  .io_uSMenq_3(1'b0),
+
+  .io_sram_w_0_addrw(sram_w_0_addrw),
+  .io_sram_w_0_dataw(sram_w_0_dataw),
+  .io_sram_w_0_enw  (sram_w_0_enw),
+  .io_sram_w_1_addrw(11'd0),
+  .io_sram_w_1_dataw(8'h0),
+  .io_sram_w_1_enw(1'b0),
+  .io_sram_w_2_addrw(11'd0),
+  .io_sram_w_2_dataw(8'h0),
+  .io_sram_w_2_enw(1'b0),
+  .io_sram_w_3_addrw(11'd0),
+  .io_sram_w_3_dataw(8'h0),
+  .io_sram_w_3_enw(1'b0),
+  .io_sram_r_0_addrr(11'd0),
+  .io_sram_r_0_datar(),
+  .io_sram_r_0_enr(1'b0),
+  .io_sram_r_1_addrr(11'd0),
+  .io_sram_r_1_datar(),
+  .io_sram_r_1_enr(1'b0),
+  .io_sram_r_2_addrr(11'd0),
+  .io_sram_r_2_datar(),
+  .io_sram_r_2_enr(1'b0),
+  .io_sram_r_3_addrr(11'd0),
+  .io_sram_r_3_datar(),
+  .io_sram_r_3_enr(1'b0),
+
+  .io_modeSel(1'b1), //主机模式
+
+  .io_req_valid      (req_valid),
+  .io_req_bits_txAddr(req_bits_txAddr),
+  .io_req_bits_rxAddr(req_bits_rxAddr),
+  .io_req_bits_length(req_bits_length),
+  .io_rsp_valid(),
+  .io_rsp_bits_isError(),
+  .io_rsp_bits_length()
+);
+
+ShinTop s_ShinTop_slv0(
+  .clock(clock),
+  .reset(reset),
+
+  .io_clk8x(clk8x),
+  .io_dDatIn(dDat_w[0]),
+  .io_dDatOut(dDat_w[1]),
+  .io_uDatIn(uDat_w[1]),
+  .io_uDatOut(uDat_w[0]),
+  
+  .io_timeStamp(timeStamp),
+
+  .io_dSMdeq_0(1'b0),
+  .io_dSMdeq_1(1'b0),
+  .io_dSMdeq_2(1'b0),
+  .io_dSMdeq_3(1'b0),
+  .io_uSMenq_0(1'b0),
+  .io_uSMenq_1(1'b0),
+  .io_uSMenq_2(1'b0),
+  .io_uSMenq_3(1'b0),
+
+  .io_sram_w_0_addrw(11'd0),
+  .io_sram_w_0_dataw(8'h0),
+  .io_sram_w_0_enw(1'b0),
+  .io_sram_w_1_addrw(11'd0),
+  .io_sram_w_1_dataw(8'h0),
+  .io_sram_w_1_enw(1'b0),
+  .io_sram_w_2_addrw(11'd0),
+  .io_sram_w_2_dataw(8'h0),
+  .io_sram_w_2_enw(1'b0),
+  .io_sram_w_3_addrw(11'd0),
+  .io_sram_w_3_dataw(8'h0),
+  .io_sram_w_3_enw(1'b0),
+  .io_sram_r_0_addrr(11'd0),
+  .io_sram_r_0_datar(),
+  .io_sram_r_0_enr(1'b0),
+  .io_sram_r_1_addrr(11'd0),
+  .io_sram_r_1_datar(),
+  .io_sram_r_1_enr(1'b0),
+  .io_sram_r_2_addrr(11'd0),
+  .io_sram_r_2_datar(),
+  .io_sram_r_2_enr(1'b0),
+  .io_sram_r_3_addrr(11'd0),
+  .io_sram_r_3_datar(),
+  .io_sram_r_3_enr(1'b0),
+
+  .io_modeSel(1'b0),
+
+  .io_req_valid(1'b0),
+  .io_req_bits_txAddr(15'h0),
+  .io_req_bits_rxAddr(15'h0),
+  .io_req_bits_length(12'd0),
+  .io_rsp_valid(),
+  .io_rsp_bits_isError(),
+  .io_rsp_bits_length()
+);
+
+ShinTop s_ShinTop_slv1(
+  .clock(clock),
+  .reset(reset),
+
+  .io_clk8x(clk8x),
+  .io_dDatIn(dDat_w[1]),
+  .io_dDatOut(dDat_w[2]),
+  .io_uDatIn(uDat_w[2]),
+  .io_uDatOut(uDat_w[1]),
+  
+  .io_timeStamp(timeStamp),
+
+  .io_dSMdeq_0(1'b0),
+  .io_dSMdeq_1(1'b0),
+  .io_dSMdeq_2(1'b0),
+  .io_dSMdeq_3(1'b0),
+  .io_uSMenq_0(1'b0),
+  .io_uSMenq_1(1'b0),
+  .io_uSMenq_2(1'b0),
+  .io_uSMenq_3(1'b0),
+
+  .io_sram_w_0_addrw(11'd0),
+  .io_sram_w_0_dataw(8'h0),
+  .io_sram_w_0_enw(1'b0),
+  .io_sram_w_1_addrw(11'd0),
+  .io_sram_w_1_dataw(8'h0),
+  .io_sram_w_1_enw(1'b0),
+  .io_sram_w_2_addrw(11'd0),
+  .io_sram_w_2_dataw(8'h0),
+  .io_sram_w_2_enw(1'b0),
+  .io_sram_w_3_addrw(11'd0),
+  .io_sram_w_3_dataw(8'h0),
+  .io_sram_w_3_enw(1'b0),
+  .io_sram_r_0_addrr(11'd0),
+  .io_sram_r_0_datar(),
+  .io_sram_r_0_enr(1'b0),
+  .io_sram_r_1_addrr(11'd0),
+  .io_sram_r_1_datar(),
+  .io_sram_r_1_enr(1'b0),
+  .io_sram_r_2_addrr(11'd0),
+  .io_sram_r_2_datar(),
+  .io_sram_r_2_enr(1'b0),
+  .io_sram_r_3_addrr(11'd0),
+  .io_sram_r_3_datar(),
+  .io_sram_r_3_enr(1'b0),
+
+  .io_modeSel(1'b0),
+
+  .io_req_valid(1'b0),
+  .io_req_bits_txAddr(15'h0),
+  .io_req_bits_rxAddr(15'h0),
+  .io_req_bits_length(12'd0),
+  .io_rsp_valid(),
+  .io_rsp_bits_isError(),
+  .io_rsp_bits_length()
+);
+
+ShinTop s_ShinTop_slv2(
+  .clock(clock),
+  .reset(reset),
+
+  .io_clk8x(clk8x),
+  .io_dDatIn(dDat_w[2]),
+  .io_dDatOut(dDat_w[3]),
+  .io_uDatIn(uDat_w[3]),
+  .io_uDatOut(uDat_w[2]),
+  
+  .io_timeStamp(timeStamp),
+
+  .io_dSMdeq_0(1'b0),
+  .io_dSMdeq_1(1'b0),
+  .io_dSMdeq_2(1'b0),
+  .io_dSMdeq_3(1'b0),
+  .io_uSMenq_0(1'b0),
+  .io_uSMenq_1(1'b0),
+  .io_uSMenq_2(1'b0),
+  .io_uSMenq_3(1'b0),
+
+  .io_sram_w_0_addrw(11'd0),
+  .io_sram_w_0_dataw(8'h0),
+  .io_sram_w_0_enw(1'b0),
+  .io_sram_w_1_addrw(11'd0),
+  .io_sram_w_1_dataw(8'h0),
+  .io_sram_w_1_enw(1'b0),
+  .io_sram_w_2_addrw(11'd0),
+  .io_sram_w_2_dataw(8'h0),
+  .io_sram_w_2_enw(1'b0),
+  .io_sram_w_3_addrw(11'd0),
+  .io_sram_w_3_dataw(8'h0),
+  .io_sram_w_3_enw(1'b0),
+  .io_sram_r_0_addrr(11'd0),
+  .io_sram_r_0_datar(),
+  .io_sram_r_0_enr(1'b0),
+  .io_sram_r_1_addrr(11'd0),
+  .io_sram_r_1_datar(),
+  .io_sram_r_1_enr(1'b0),
+  .io_sram_r_2_addrr(11'd0),
+  .io_sram_r_2_datar(),
+  .io_sram_r_2_enr(1'b0),
+  .io_sram_r_3_addrr(11'd0),
+  .io_sram_r_3_datar(),
+  .io_sram_r_3_enr(1'b0),
+
+  .io_modeSel(1'b0),
+
+  .io_req_valid(1'b0),
+  .io_req_bits_txAddr(15'h0),
+  .io_req_bits_rxAddr(15'h0),
+  .io_req_bits_length(12'd0),
+  .io_rsp_valid(),
+  .io_rsp_bits_isError(),
+  .io_rsp_bits_length()
+);
+
+ShinTop s_ShinTop_slv3(
+  .clock(clock),
+  .reset(reset),
+
+  .io_clk8x(clk8x),
+  .io_dDatIn(dDat_w[3]),
+  .io_dDatOut(),
+  .io_uDatIn(1'b0),
+  .io_uDatOut(uDat_w[3]),
+  
+  .io_timeStamp(timeStamp),
+
+  .io_dSMdeq_0(1'b0),
+  .io_dSMdeq_1(1'b0),
+  .io_dSMdeq_2(1'b0),
+  .io_dSMdeq_3(1'b0),
+  .io_uSMenq_0(1'b0),
+  .io_uSMenq_1(1'b0),
+  .io_uSMenq_2(1'b0),
+  .io_uSMenq_3(1'b0),
+
+  .io_sram_w_0_addrw(11'd0),
+  .io_sram_w_0_dataw(8'h0),
+  .io_sram_w_0_enw(1'b0),
+  .io_sram_w_1_addrw(11'd0),
+  .io_sram_w_1_dataw(8'h0),
+  .io_sram_w_1_enw(1'b0),
+  .io_sram_w_2_addrw(11'd0),
+  .io_sram_w_2_dataw(8'h0),
+  .io_sram_w_2_enw(1'b0),
+  .io_sram_w_3_addrw(11'd0),
+  .io_sram_w_3_dataw(8'h0),
+  .io_sram_w_3_enw(1'b0),
+  .io_sram_r_0_addrr(11'd0),
+  .io_sram_r_0_datar(),
+  .io_sram_r_0_enr(1'b0),
+  .io_sram_r_1_addrr(11'd0),
+  .io_sram_r_1_datar(),
+  .io_sram_r_1_enr(1'b0),
+  .io_sram_r_2_addrr(11'd0),
+  .io_sram_r_2_datar(),
+  .io_sram_r_2_enr(1'b0),
+  .io_sram_r_3_addrr(11'd0),
+  .io_sram_r_3_datar(),
+  .io_sram_r_3_enr(1'b0),
+
+  .io_modeSel(1'b0),
+
+  .io_req_valid(1'b0),
+  .io_req_bits_txAddr(15'h0),
+  .io_req_bits_rxAddr(15'h0),
+  .io_req_bits_length(12'd0),
+  .io_rsp_valid(),
+  .io_rsp_bits_isError(),
+  .io_rsp_bits_length()
+);
+
+
+
+always @(posedge clock) begin
+  timeStamp <= timeStamp + 64'd1;
+end
+
+
+
+
+
+
+
+initial begin
+	clock = 0;
+  clk8x = 0;
+	reset = 0;
+
+	#100
+	reset <= 1;
+
+	#240
+	reset <= 0;
+
+#3000000
+	$display("Time Out !!!");
+	$stop;
+end
+
+initial begin
+	forever begin #10 clk8x <= ~clk8x; end
+end
+
+initial begin
+	forever begin #80 clock <= ~clock; end
+end
+
+initial
+begin
+	$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
+	$dumpvars(0, ShinTopTb);//tb模块名称
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  reg [7:0] dataBuf[0:2047];
+
+  initial begin
+
+  end
+
+
+
+    // for( integer i = 0; i < 8; i = i + 1 ) begin
+    //   if( i != 5 ) begin
+
+    //     dataBuf[3 + 64 * i + 0] = $random; 
+    //     dataBuf[3 + 64 * i + 1] = $random;
+    //     dataBuf[3 + 64 * i + 2] = $random;
+    //     dataBuf[3 + 64 * i + 3] = $random;
+    //     dataBuf[3 + 64 * i + 4] = 8'h0;
+    //     dataBuf[3 + 64 * i + 5] = 8'd56;
+    //     dataBuf[3 + 64 * i + 6] = $random;
+    //     dataBuf[3 + 64 * i + 7] = $random;
+
+
+    //   end
+  // end
+
+
+initial begin
+
+  //嗅探
+  #10000
+
+  begin
+    dataBuf[0] = 8'h00;
+    dataBuf[1] = 8'h01;//heeader length 0 嗅探包1
+    dataBuf[2] = 8'h00;
+    dataBuf[3] = 8'h00;
+
+    //无子报文
+
+    //装填sram
+    for( integer i = 0; i < 4; i = i + 1 ) begin
+      @(posedge clock) #3
+      sram_w_0_enw = 1'b1;
+      sram_w_0_addrw = i;
+      sram_w_0_dataw = dataBuf[i];
+    end
+
+    @(posedge clock) #3
+    sram_w_0_enw = 1'b0;
+    sram_w_0_addrw = 15'h0;
+    sram_w_0_dataw = 8'h0;
+
+    //提交SM
+    @(posedge clock) #3
+    txCmf = 1'b1;
+    @(posedge clock) #3
+    txCmf = 1'b0;
+
+    //发布请求
+    @(posedge clock) #3
+    req_valid = 1'b1;
+    req_bits_txAddr = 0;
+    req_bits_rxAddr = 0;
+    req_bits_length = 4;
+
+    @(posedge clock) #3
+    req_valid = 1'b0;
+
+  end
+
+
+
+
+
+
+
+  // 顺序索引
+  #50000
+  #50000
+  #50000
+
+
+  begin
+
+    dataBuf[0] = 8'h00;
+    dataBuf[1] = 8'ha0;//heeader length 10
+    dataBuf[2] = 8'h00;
+    dataBuf[3] = 8'h00;
+
+    //子报文
+    //设置顺序地址
+    dataBuf[4] = 8'h0; //设备索引
+    dataBuf[5] = 8'h0; //设备索引、类型
+    dataBuf[6] = $random; //地址
+    dataBuf[7] = $random; //地址
+    dataBuf[8] = 8'hd0;   //命令d 负载长度2
+    dataBuf[9] = 8'd02;   //负载长度2
+    dataBuf[10] = 8'h0;   //工作计数0
+    dataBuf[11] = 8'h0;   //工作计数0
+
+    dataBuf[12] = 8'h0;   //负载
+    dataBuf[13] = 8'h0;   //负载
+
+
+
+    for( integer i = 0; i < 14; i = i + 1 ) begin
+      @(posedge clock) #3
+      sram_w_0_enw = 1'b1;
+      sram_w_0_addrw = i;
+      sram_w_0_dataw = dataBuf[i];
+    end
+
+    @(posedge clock) #3
+    sram_w_0_enw = 1'b0;
+    sram_w_0_addrw = 15'h0;
+    sram_w_0_dataw = 8'h0;
+
+    @(posedge clock) #3
+    txCmf = 1'b1;
+    @(posedge clock) #3
+    txCmf = 1'b0;
+
+    @(posedge clock) #3
+    req_valid = 1'b1;
+    req_bits_txAddr = 0;
+    req_bits_rxAddr = 0;
+    req_bits_length = 14;
+
+    @(posedge clock) #3
+    req_valid = 1'b0;
+
+  end
+
+
+  //读写
+  #50000
+  #50000
+  #50000
+  #50000
+  
+  begin
+
+    dataBuf[0] = 8'h20;
+    dataBuf[1] = 8'h00;//heeader length 512
+    dataBuf[2] = 8'h00;
+    dataBuf[3] = 8'h00;
+
+    //子报文
+    dataBuf[4] = 8'h0; 
+    dataBuf[5] = 8'h8; //index = 2
+
+    dataBuf[6] = 8'h08; //地址 //SM0
+    dataBuf[7] = 8'h30; //地址 //偏置
+
+    dataBuf[8] = 8'h20; //命令2 长度56
+    dataBuf[9] = 8'd56; //长度
+    dataBuf[10] = $random;
+    dataBuf[11] = $random;
+
+    for( integer j = 0; j < 64-8; j = j + 1 ) begin
+      @(posedge clock) #3 
+      dataBuf[12+j] = $random;
+    end
+
+    //-------------------------
+
+    //子报文
+    dataBuf[68] = 8'h0; 
+    dataBuf[69] = 8'h4; //index = 1
+
+    dataBuf[70] = 8'h08; //地址 //SM0
+    dataBuf[71] = 8'h40; //地址 //偏置
+
+    dataBuf[72] = 8'h10; //命令1 长度56
+    dataBuf[73] = 8'd56; //长度
+    dataBuf[74] = $random;
+    dataBuf[75] = $random;
+
+    for( integer j = 0; j < 64-8; j = j + 1 ) begin
+      @(posedge clock) #3 
+      dataBuf[76+j] = $random;
+    end
+
+    //-------------------------
+
+    //子报文
+    dataBuf[132] = 8'h0; 
+    dataBuf[133] = 8'hc; //index = 3
+
+    dataBuf[134] = 8'h09; //地址 //SM1
+    dataBuf[135] = 8'h40; //地址 //偏置
+
+    dataBuf[136] = 8'h00; //命令0 长度56
+    dataBuf[137] = 8'd56; //长度
+    dataBuf[138] = $random;
+    dataBuf[139] = $random;
+
+    for( integer j = 0; j < 64-8; j = j + 1 ) begin
+      @(posedge clock) #3 
+      dataBuf[140+j] = $random;
+    end
+
+    //-------------------------
+
+    for( integer i = 0 ; i < 5; i = i + 1) begin
+      //子报文
+      dataBuf[196+i*64+0] = $random;
+      dataBuf[196+i*64+1] = 8'h0; //index = random
+
+      dataBuf[196+i*64+2] = $random;
+      dataBuf[196+i*64+3] = $random;
+
+      dataBuf[196+i*64+4] = 8'h00; //命令0 长度56
+      dataBuf[196+i*64+5] = 8'd56; //长度
+      dataBuf[196+i*64+6] = $random;
+      dataBuf[196+i*64+7] = $random;
+
+      for( integer j = 0; j < 64-8; j = j + 1 ) begin
+        @(posedge clock) #3 
+        dataBuf[196+i*64+8+j] = $random;
+      end
+    end
+
+    for( integer i = 0; i < 516; i = i + 1 ) begin
+      @(posedge clock) #3
+      sram_w_0_enw = 1'b1;
+      sram_w_0_addrw = i;
+      sram_w_0_dataw = dataBuf[i];
+    end
+
+    @(posedge clock) #3
+    sram_w_0_enw = 1'b0;
+    sram_w_0_addrw = 15'h0;
+    sram_w_0_dataw = 8'h0;
+
+    @(posedge clock) #3
+    txCmf = 1'b1;
+    @(posedge clock) #3
+    txCmf = 1'b0;
+
+    @(posedge clock) #3
+    req_valid = 1'b1;
+    req_bits_txAddr = 0;
+    req_bits_rxAddr = 0;
+    req_bits_length = 516;
+
+    @(posedge clock) #3
+    req_valid = 1'b0;
+  end
+
+
+
+  // 同步
+  #90000
+  #90000
+  #90000
+  #90000
+  #90000
+  #90000
+  #90000
+  #90000
+  #90000  
+  #90000
+  #90000
+  #90000
+  #90000
+  #90000
+
+
+  begin
+
+    dataBuf[0] = 8'h01;
+    dataBuf[1] = 8'h40;//heeader length 20
+    dataBuf[2] = 8'h00;
+    dataBuf[3] = 8'h00;
+
+    //子报文
+    //设置同步
+    dataBuf[4] = 8'h0; //设备索引
+    dataBuf[5] = 8'h0; //设备索引、类型
+    dataBuf[6] = $random; //地址
+    dataBuf[7] = $random; //地址
+    dataBuf[8] = 8'he0;   //命令d 负载长度2
+    dataBuf[9] = 8'h0c;   //负载长度c
+    dataBuf[10] = 8'h0;   //工作计数0
+    dataBuf[11] = 8'h0;   //工作计数0
+
+    dataBuf[12] = timeStamp[7:0];   //负载
+    dataBuf[13] = timeStamp[15:8];   //负载
+    dataBuf[14] = timeStamp[23:16];   //负载
+    dataBuf[15] = timeStamp[31:24];   //负载
+    dataBuf[16] = timeStamp[39:32];   //负载
+    dataBuf[17] = timeStamp[47:40];   //负载
+    dataBuf[18] = timeStamp[55:48];   //负载
+    dataBuf[19] = timeStamp[63:56];   //负载
+
+    dataBuf[20] = s_ShinTop_Mst.masterParser.deltaTimeStamp[ 7: 0];   //负载
+    dataBuf[21] = s_ShinTop_Mst.masterParser.deltaTimeStamp[15: 8];   //负载
+    dataBuf[22] = s_ShinTop_Mst.masterParser.deltaTimeStamp[23:16];   //负载
+    dataBuf[23] = s_ShinTop_Mst.masterParser.deltaTimeStamp[31:24];   //负载
+
+    for( integer i = 0; i < 24; i = i + 1 ) begin
+      @(posedge clock) #3
+      sram_w_0_enw = 1'b1;
+      sram_w_0_addrw = i;
+      sram_w_0_dataw = dataBuf[i];
+    end
+
+    @(posedge clock) #3
+    sram_w_0_enw = 1'b0;
+    sram_w_0_addrw = 15'h0;
+    sram_w_0_dataw = 8'h0;
+
+    @(posedge clock) #3
+    txCmf = 1'b1;
+    @(posedge clock) #3
+    txCmf = 1'b0;
+
+    @(posedge clock) #3
+    req_valid = 1'b1;
+    req_bits_txAddr = 0;
+    req_bits_rxAddr = 0;
+    req_bits_length = 24;
+
+    @(posedge clock) #3
+    req_valid = 1'b0;
+
+  end
+
+
+end
+
+
+endmodule
+