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执行第一个task块

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This commit is contained in:
Ruige Lee
2025-05-12 15:41:11 +08:00
parent e079103037
commit afa1b9864f
5 changed files with 542 additions and 13 deletions
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8
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -70,8 +70,8 @@ class SpiInterface extends Module{
// spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
io.isEnR := isSckPosedgeNext(0) & isSpiRead
io.isEnW := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite
io.isEnR := isSckPosedgeNext(0) & bitSel === 0.U & byteSel >= 3.U & isSpiRead
io.isEnW := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -90,7 +90,9 @@ class SpiInterface extends Module{
when( byteSel === 0.U || byteSel === 1.U) { //CS为低，且SCK上跳的第0byte
addrSel := Cat( addrSel(14,0), shiftMOSI(1) )
} .otherwise{ // byteSel > 1.U
addrSel := addrSel + 1.U
when( isSckPosedgeNext(1) & byteSel >= 3.U & bitSel === 0.U ){
addrSel := addrSel + 1.U
}
}
}