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执行第一个task块

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This commit is contained in:
Ruige Lee
2025-05-12 15:41:11 +08:00
parent e079103037
commit afa1b9864f
5 changed files with 542 additions and 13 deletions
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12
src/main/scala/backBoard/shin/Interface.scala
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@@ -246,20 +246,16 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
val dataw: UInt
val isEnR: Bool
mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
for( i <- 0 until 8 ){
cReg.smEnqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) )
)
cReg.smDeqAddr(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) )
)
}