diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 59bd942..a82ac3e 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -379,13 +379,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       Seq(
         //本地时钟
         (addr === "h100".U )  -> cReg.timeStamp(7,0),
-        (addr === "h101".U )  -> RegEnable(cReg.timeStamp(15,8),  isEnR & addrr === "h100".U),
-        (addr === "h102".U )  -> RegEnable(cReg.timeStamp(23,16), isEnR & addrr === "h100".U),
-        (addr === "h103".U )  -> RegEnable(cReg.timeStamp(31,24), isEnR & addrr === "h100".U),
-        (addr === "h104".U )  -> RegEnable(cReg.timeStamp(39,32), isEnR & addrr === "h100".U),
-        (addr === "h105".U )  -> RegEnable(cReg.timeStamp(47,40), isEnR & addrr === "h100".U),
-        (addr === "h106".U )  -> RegEnable(cReg.timeStamp(55,48), isEnR & addrr === "h100".U),
-        (addr === "h107".U )  -> RegEnable(cReg.timeStamp(63,56), isEnR & addrr === "h100".U),
+        (addr === "h101".U )  -> RegEnable(cReg.timeStamp(15,8),  isEnR & (addrr === "h100".U)),
+        (addr === "h102".U )  -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)),
+        (addr === "h103".U )  -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)),
+        (addr === "h104".U )  -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)),
+        (addr === "h105".U )  -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)),
+        (addr === "h106".U )  -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)),
+        (addr === "h107".U )  -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)),
 
         //参考主站时钟
         (addr === "h108".U & isSlvMode)  -> sReg.deltaFinal(7,0),
@@ -411,13 +411,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
 
         //校准后的时钟
         (addr === "h118".U )  -> cReg.recoTimeStamp(7,0),
-        (addr === "h119".U )  -> cReg.recoTimeStamp(15,8),
-        (addr === "h11a".U )  -> cReg.recoTimeStamp(23,16),
-        (addr === "h11b".U )  -> cReg.recoTimeStamp(31,24),
-        (addr === "h11c".U )  -> cReg.recoTimeStamp(39,32),
-        (addr === "h11d".U )  -> cReg.recoTimeStamp(47,40),
-        (addr === "h11e".U )  -> cReg.recoTimeStamp(55,48),
-        (addr === "h11f".U )  -> cReg.recoTimeStamp(63,56),
+        (addr === "h119".U )  -> RegEnable(cReg.recoTimeStamp(15,8),  isEnR & (addrr === "h118".U)),
+        (addr === "h11a".U )  -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)),
+        (addr === "h11b".U )  -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)),
+        (addr === "h11c".U )  -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)),
+        (addr === "h11d".U )  -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)),
+        (addr === "h11e".U )  -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)),
+        (addr === "h11f".U )  -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)),
 
         (addr === "h120".U )  -> cReg.syncCfg,