4b5b 8b10b接线完成

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -4,19 +4,24 @@ import chisel3._
 import chisel3.util._
 
 
+
+
+
+
 //work in 100MHZ
 class CDRInIO extends Bundle{
   val axis = Decoupled(new AXIS_Bundle(8))
+  val decode = Flipped(new Decode_Bundle)
   val serDat = Input(Bool())
   val flush = Input(Bool())
 }
 
 
+
+
 abstract class CDRInBase extends Module with RequireAsyncReset{
-
-
   val io: CDRInIO = IO(new CDRInIO)
-
+  io.decode.dataIn := 0.U
 
   val syncSerDat = Wire(Bool())
 }
@@ -144,8 +149,8 @@ trait CDRInAxis{ this: CDRInBase =>
 
   def HeaderByte: Int = 4
 
-  val ETH_PRE = "b1100010001".U(10.W)
+  val ETH_PRE = "h68".U(8.W)
-  val ETH_SFD = "b0110100111".U(10.W)
+  val ETH_SFD = "h25".U(8.W)
 
   val STATE_IDLE = 0.U
   val STATE_HEADER = 1.U
@@ -157,15 +162,17 @@ trait CDRInAxis{ this: CDRInBase =>
   val bitCnt = RegInit(0.U(4.W))
   val byteCnt = RegInit(0.U((12+1).W))
 
-  val checkSFD = RegInit( 0.U(20.W) )
+  val checkSFD = RegInit( 0.U(10.W) )
 
   when( io.flush ){
     checkSFD := 0.U
   } .otherwise{
-    checkSFD := Cat( checkSFD(18,0), syncSerDat )
+    checkSFD := Cat( checkSFD(8,0), syncSerDat )
   }
 
-  val shiftData = Dualb4b5Decoder(checkSFD(9,0))
+  io.decode.dataIn := checkSFD(9,0)
+  val shiftData = io.decode.dataOut
+  val shiftDataNext = RegNext( shiftData, 0.U(8.W) )
 
   val payloadLen = RegInit(0.U(12.W))
 
@@ -180,7 +187,7 @@ trait CDRInAxis{ this: CDRInBase =>
   stateNext := 
     Mux( io.flush, STATE_IDLE,
       Mux1H(Seq(
-        (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
+        (stateCurr === STATE_IDLE)    -> ( Mux( shiftDataNext === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
         (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
         (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U)  ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD  )), // PAYLOAD
       ))                                                                  //crc
@@ -190,7 +197,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
 
 
-  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
+  when( stateCurr === STATE_IDLE & ( shiftDataNext === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
     bitCnt := 0.U
   } .otherwise{
     when( bitCnt === 9.U ){
@@ -202,7 +209,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
   when( io.flush ){
     byteCnt := 0.U
-  } .elsewhen( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
+  } .elsewhen( stateCurr === STATE_IDLE & ( shiftDataNext === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
     byteCnt := 0.U
   } .elsewhen( bitCnt === 9.U ){
     when( stateCurr === STATE_HEADER ){

src/main/scala/backBoard/ebus/CDROut.scala

@@ -9,14 +9,20 @@ class AXIS_Bundle(dw: Int) extends Bundle{
   val tuser = Bool()
 }
 
+
+
+
 //work in 100MHZ
 class CDROutIO extends Bundle{
   val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
+  val encode = Flipped(new Encode_Bundle)
   val serDat = Output(Bool())
 
+
   val flush = Input(Bool())
 
 
+
 }
 
 
@@ -29,8 +35,8 @@ class CDROut extends Module with RequireAsyncReset{
   def STATE_PREAMBLE = 1.U
   def STATE_PAYLOAD = 2.U
 
-  val ETH_PRE = "b1100010001".U(10.W)
+  val ETH_PRE = "h68".U(8.W)
-  val ETH_SFD = "b0110100111".U(10.W)
+  val ETH_SFD = "h25".U(8.W)
 
   val stateNext = Wire(UInt(2.W))
   val stateCurr = RegNext( stateNext, 0.U )
@@ -40,6 +46,8 @@ class CDROut extends Module with RequireAsyncReset{
   val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
 
   val shiftData = RegInit(0.U(10.W))
+  io.encode.isEnable := false.B    //组合逻辑
+  io.encode.dataIn := 0.U     //组合逻辑
 
   stateNext := 
     Mux( io.flush, STATE_IDLE,
@@ -65,18 +73,24 @@ class CDROut extends Module with RequireAsyncReset{
   when( io.flush ){
     shiftData := 0.U
   } .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
-    shiftData := ETH_PRE
+    shiftData := io.encode.dataOut
+    io.encode.dataIn := ETH_PRE   //组合逻辑
+    io.encode.isEnable := true.B  //组合逻辑
   } .otherwise{
     when( bitCnt =/= 9.U ){
       shiftData := shiftData << 1
     } .otherwise{ //bitCnt === 9.U
       when( stateCurr === STATE_PREAMBLE ){
-        shiftData := MuxCase( ETH_PRE, Array(
+        shiftData := io.encode.dataOut
+        io.encode.dataIn := MuxCase( ETH_PRE, Array(
           ( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
-          ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
+          ( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata,
-        ))
+        ))  //组合逻辑
+        io.encode.isEnable := true.B    //组合逻辑
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
-        shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
+        io.encode.dataIn := io.axis.bits.tdata  //组合逻辑
+        shiftData := io.encode.dataOut
+        io.encode.isEnable := true.B    //组合逻辑
       }
     }
   }

src/main/scala/backBoard/ebus/b4b5.scala

@@ -66,20 +66,13 @@ object Dualb4b5Decoder{
 
 
 class b4b5DualEncode extends Module with RequireAsyncReset{
-  val io = IO(new Bundle{
+  val io = IO(new Encode_Bundle)
-    val dataIn = Input(UInt(8.W))
-    val isEnable = Input(Bool())
-    val dataOut = Output(UInt(10.W))
-  })
 
   io.dataOut := Dualb4b5Encoder(io.dataIn)
 }
 
-class b8b10Decode extends Module with RequireAsyncReset{
+class b4b5DualDecode extends Module with RequireAsyncReset{
-  val io = IO(new Bundle{
+  val io = IO(new Decode_Bundle)
-    val dataIn = Input(UInt(10.W))
-    val dataOut = Output(UInt(8.W))
-  })
 
   io.dataOut := Dualb4b5Decoder(io.dataIn)
 }

src/main/scala/backBoard/ebus/b8b10.scala

@@ -3,13 +3,19 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+class Encode_Bundle extends Bundle{
+  val dataIn   = Input(UInt(8.W))
+  val isEnable = Input(Bool())
+  val dataOut  = Output(UInt(10.W))
+}
+
+class Decode_Bundle extends Bundle{
+  val dataIn   = Input(UInt(10.W))
+  val dataOut  = Output(UInt(8.W))
+}
 
 class b8b10Encode extends Module with RequireAsyncReset{
-  val io = IO(new Bundle{
+  val io = IO(new Encode_Bundle)
-    val dataIn = Input(UInt(8.W))
-    val isEnable = Input(Bool())
-    val dataOut = Output(UInt(10.W))
-  })
 
   val rd = RegInit(false.B)
 
@@ -49,19 +55,6 @@ class b8b10Encode extends Module with RequireAsyncReset{
     (io.dataIn(4,0) === "b11111".U) -> Mux( rd, "b101011".U(6.W), "b010100".U(6.W) )
   ))
 
-  val b3b4LookUp = Mux1H(Seq(
-    (io.dataIn(7,5) === "b000".U) -> Mux( b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
-    (io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
-    (io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
-    (io.dataIn(7,5) === "b011".U) -> Mux( b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
-    (io.dataIn(7,5) === "b100".U) -> Mux( b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
-    (io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
-    (io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
-    (io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ),
-      ((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W),  // 17, 18, 20 are special cases
-      ((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) &  b5b6RD) -> "b1000".U(4.W),  // 11, 13, 14 are special cases 
-    )
-  ))
 
   val b5b6RD = Mux1H(Seq(
     (io.dataIn(4,0) === "b00000".U) -> ~rd,
@@ -71,7 +64,7 @@ class b8b10Encode extends Module with RequireAsyncReset{
     (io.dataIn(4,0) === "b00100".U) -> ~rd,
     (io.dataIn(4,0) === "b00101".U) ->  rd,
     (io.dataIn(4,0) === "b00110".U) ->  rd,
-    (io.dataIn(4,0) === "b00111".U) ->  rd
+    (io.dataIn(4,0) === "b00111".U) ->  rd,
     (io.dataIn(4,0) === "b01000".U) -> ~rd,
     (io.dataIn(4,0) === "b01001".U) ->  rd,
     (io.dataIn(4,0) === "b01010".U) ->  rd,
@@ -98,6 +91,20 @@ class b8b10Encode extends Module with RequireAsyncReset{
     (io.dataIn(4,0) === "b11111".U) -> ~rd,
   ))
 
+  val b3b4LookUp = Mux1H(Seq(
+    (io.dataIn(7,5) === "b000".U) -> Mux( b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
+    (io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
+    (io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
+    (io.dataIn(7,5) === "b011".U) -> Mux( b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
+    (io.dataIn(7,5) === "b100".U) -> Mux( b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
+    (io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
+    (io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
+    (io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
+      ((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W),  // 17, 18, 20 are special cases
+      ((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) &  b5b6RD) -> "b1000".U(4.W),  // 11, 13, 14 are special cases 
+    ))
+  ))
+
   val b3b4RD = Mux1H(Seq(
     (io.dataIn(7,5) === "b000".U) -> ~b5b6RD,
     (io.dataIn(7,5) === "b001".U) ->  b5b6RD,
@@ -126,42 +133,39 @@ class b8b10Encode extends Module with RequireAsyncReset{
 
 
 class b8b10Decode extends Module with RequireAsyncReset{
-  val io = IO(new Bundle{
+  val io = IO(new Decode_Bundle)
-    val dataIn = Input(UInt(10.W))
-    val dataOut = Output(UInt(8.W))
-  })
 
 
   val b5b6LookUp = Mux1H(Seq(
     (io.dataIn(9,4) === "b100111".U(6.W) || io.dataIn(9,4) === "b011000".U(6.W) ) -> "b00000".U, 
     (io.dataIn(9,4) === "b011101".U(6.W) || io.dataIn(9,4) === "b100010".U(6.W) ) -> "b00001".U, 
     (io.dataIn(9,4) === "b101101".U(6.W) || io.dataIn(9,4) === "b010010".U(6.W) ) -> "b00010".U, 
-    (io.dataIn(9,4) === "b110001".U(6.W),)                              -> "b00011".U, 
+    (io.dataIn(9,4) === "b110001".U(6.W))                              -> "b00011".U, 
     (io.dataIn(9,4) === "b110101".U(6.W) || io.dataIn(9,4) === "b001010".U(6.W) ) -> "b00100".U, 
-    (io.dataIn(9,4) === "b101001".U(6.W),)                              -> "b00101".U, 
+    (io.dataIn(9,4) === "b101001".U(6.W))                              -> "b00101".U, 
-    (io.dataIn(9,4) === "b011001".U(6.W),)                              -> "b00110".U, 
+    (io.dataIn(9,4) === "b011001".U(6.W))                              -> "b00110".U, 
     (io.dataIn(9,4) === "b111000".U(6.W) || io.dataIn(9,4) === "b000111".U(6.W) ) -> "b00111".U, 
     (io.dataIn(9,4) === "b111001".U(6.W) || io.dataIn(9,4) === "b000110".U(6.W) ) -> "b01000".U, 
-    (io.dataIn(9,4) === "b100101".U(6.W),)                              -> "b01001".U, 
+    (io.dataIn(9,4) === "b100101".U(6.W))                              -> "b01001".U, 
-    (io.dataIn(9,4) === "b010101".U(6.W),)                              -> "b01010".U, 
+    (io.dataIn(9,4) === "b010101".U(6.W))                              -> "b01010".U, 
-    (io.dataIn(9,4) === "b110100".U(6.W),)                              -> "b01011".U, 
+    (io.dataIn(9,4) === "b110100".U(6.W))                              -> "b01011".U, 
-    (io.dataIn(9,4) === "b001101".U(6.W),)                              -> "b01100".U, 
+    (io.dataIn(9,4) === "b001101".U(6.W))                              -> "b01100".U, 
-    (io.dataIn(9,4) === "b101100".U(6.W),)                              -> "b01101".U, 
+    (io.dataIn(9,4) === "b101100".U(6.W))                              -> "b01101".U, 
-    (io.dataIn(9,4) === "b011100".U(6.W),)                              -> "b01110".U, 
+    (io.dataIn(9,4) === "b011100".U(6.W))                              -> "b01110".U, 
     (io.dataIn(9,4) === "b010111".U(6.W) || io.dataIn(9,4) === "b101000".U(6.W) ) -> "b01111".U, 
     (io.dataIn(9,4) === "b011011".U(6.W) || io.dataIn(9,4) === "b100100".U(6.W) ) -> "b10000".U, 
-    (io.dataIn(9,4) === "b100011".U(6.W),)                              -> "b10001".U, 
+    (io.dataIn(9,4) === "b100011".U(6.W))                              -> "b10001".U, 
-    (io.dataIn(9,4) === "b010011".U(6.W),)                              -> "b10010".U, 
+    (io.dataIn(9,4) === "b010011".U(6.W))                              -> "b10010".U, 
-    (io.dataIn(9,4) === "b110010".U(6.W),)                              -> "b10011".U, 
+    (io.dataIn(9,4) === "b110010".U(6.W))                              -> "b10011".U, 
-    (io.dataIn(9,4) === "b001011".U(6.W),)                              -> "b10100".U, 
+    (io.dataIn(9,4) === "b001011".U(6.W))                              -> "b10100".U, 
-    (io.dataIn(9,4) === "b101010".U(6.W),)                              -> "b10101".U, 
+    (io.dataIn(9,4) === "b101010".U(6.W))                              -> "b10101".U, 
-    (io.dataIn(9,4) === "b011010".U(6.W),)                              -> "b10110".U, 
+    (io.dataIn(9,4) === "b011010".U(6.W))                              -> "b10110".U, 
     (io.dataIn(9,4) === "b111010".U(6.W) || io.dataIn(9,4) === "b000101".U(6.W) ) -> "b10111".U, 
     (io.dataIn(9,4) === "b110011".U(6.W) || io.dataIn(9,4) === "b001100".U(6.W) ) -> "b11000".U, 
-    (io.dataIn(9,4) === "b100110".U(6.W),)                              -> "b11001".U, 
+    (io.dataIn(9,4) === "b100110".U(6.W))                              -> "b11001".U, 
-    (io.dataIn(9,4) === "b010110".U(6.W),)                              -> "b11010".U, 
+    (io.dataIn(9,4) === "b010110".U(6.W))                              -> "b11010".U, 
     (io.dataIn(9,4) === "b110110".U(6.W) || io.dataIn(9,4) === "b001001".U(6.W) ) -> "b11011".U, 
-    (io.dataIn(9,4) === "b001110".U(6.W),)                              -> "b11100".U, 
+    (io.dataIn(9,4) === "b001110".U(6.W))                              -> "b11100".U, 
     (io.dataIn(9,4) === "b101110".U(6.W) || io.dataIn(9,4) === "b010001".U(6.W) ) -> "b11101".U, 
     (io.dataIn(9,4) === "b011110".U(6.W) || io.dataIn(9,4) === "b100001".U(6.W) ) -> "b11110".U, 
     (io.dataIn(9,4) === "b101011".U(6.W) || io.dataIn(9,4) === "b010100".U(6.W) ) -> "b11111".U, 

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -58,9 +58,15 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   val slaveParser  = Module(new SlaveParser )
   val masterParser = Module(new MasterParser)
 
+  val b4b5DownEncoder = Module(new b4b5DualEncode)
+  val b4b5DownDecoder = Module(new b4b5DualDecode)
+  val b4b5UpEncoder = Module(new b4b5DualEncode)
+  val b4b5UpDecoder = Module(new b4b5DualDecode)
 
-
+  val b8b10DownEncoder = Module(new b8b10Encode)
-
+  val b8b10DownDecoder = Module(new b8b10Decode)
+  val b8b10UpEncoder = Module(new b8b10Encode)
+  val b8b10UpDecoder = Module(new b8b10Decode)
 
 
   val interface = Module(new Interface)
@@ -504,15 +510,9 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
 
 }
 
-
+trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
-
-class MstSlvSwitch extends MstSlvSwitchBase
-with MstSlvSwitchMaster
-with MstSlvSwitchSlave
-with MstSlvSwitchWatchDog{
   val isDwUpEx = interface.io.cReg.dwupEx(15,8) === "h58".U && interface.io.cReg.dwupEx.extract(0)
 
-
   when( ~isDwUpEx ){ //未交叉
     when( interface.io.cReg.modeSel === false.B ){ //slave
       when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
@@ -579,6 +579,49 @@ with MstSlvSwitchWatchDog{
       io.dDatOut := false.B
     }
   }
+}
+
+trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
+  val isUsing8b10b = interface.io.cReg.b8b4Sel(15,8) === "h59".U && interface.io.cReg.b8b4Sel.extract(0)
+
+  when( isUsing8b10b ){
+    b8b10DownEncoder.io <> io.downCDROut.encode
+    b8b10DownDecoder.io <> io.downCDRIn.decode
+    b8b10UpEncoder.io   <> io.upCDROut.encode
+    b8b10UpDecoder.io   <> io.upCDRIn.decode
+
+    b4b5DownEncoder.io.isEnable := false.B
+    b4b5DownEncoder.io.dataIn := 0.U
+    b4b5DownDecoder.io.dataIn := 0.U
+    b4b5UpEncoder.io.isEnable := false.B
+    b4b5UpEncoder.io.dataIn := 0.U
+    b4b5UpDecoder.io.dataIn := 0.U
+  } .otherwise{
+    b4b5DownEncoder.io <> io.downCDROut.encode
+    b4b5DownDecoder.io <> io.downCDRIn.decode
+    b4b5UpEncoder.io <> io.upCDROut.encode
+    b4b5UpDecoder.io <> io.upCDRIn.decode
+
+    b8b10DownEncoder.io.isEnable := false.B
+    b8b10DownEncoder.io.dataIn := 0.U
+    b8b10DownDecoder.io.dataIn := 0.U
+    b8b10UpEncoder.io.isEnable := false.B
+    b8b10UpEncoder.io.dataIn := 0.U
+    b8b10UpDecoder.io.dataIn := 0.U
+  }
+}
+
+class MstSlvSwitch extends MstSlvSwitchBase
+with MstSlvSwitchMaster
+with MstSlvSwitchSlave
+with MstSlvSwitchWatchDog
+with MstSlvSwitchDataPath
+with MstSlvSwitchB8B4{
+
+
+
+
+
 
 
 

src/test/scala/SimCDR.scala

@@ -27,6 +27,13 @@ class SimCDR extends Module with RequireAsyncReset{
   val dataCnt = RegInit(0.U(12.W))
   val payloadLen = RegInit(("hFFF".U)(12.W))
 
+  val b4b5Encoder = Module(new b4b5DualEncode)
+  val b4b5Decoder = Module(new b4b5DualDecode)
+
+  val b8b10Encoder = Module(new b8b10Encode)
+  val b8b10Decoder = Module(new b8b10Decode)
+
+
    
   when( cdrOut.io.axis.fire & dataCnt === 0.U ){
     payloadLen := Cat( io.data, 0.U(4.W) )
@@ -72,6 +79,28 @@ class SimCDR extends Module with RequireAsyncReset{
   io.isFailed  := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
   io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
 
+
+
+
+  val isUsing8b10b = true.B
+
+
+  when( isUsing8b10b ){
+    b8b10Encoder.io <> cdrOut.io.encode
+    b8b10Decoder.io <> cdrIn.io.decode
+
+    b4b5Encoder.io.isEnable := false.B
+    b4b5Encoder.io.dataIn := 0.U
+    b4b5Decoder.io.dataIn := 0.U
+  } .otherwise{
+    b4b5Encoder.io <> cdrOut.io.encode
+    b4b5Decoder.io <> cdrIn.io.decode
+
+    b8b10Encoder.io.isEnable := false.B
+    b8b10Encoder.io.dataIn := 0.U
+    b8b10Decoder.io.dataIn := 0.U
+  }
+
 }